Clifford Wolf
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638be461c3
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Fix mem2reg handling of memories with upto data ports, fixes #888
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-21 22:21:17 +01:00 |
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Clifford Wolf
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da42f10765
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Improve "read_verilog -dump_vlog[12]" handling of upto ranges
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-21 22:20:16 +01:00 |
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Clifford Wolf
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9b0e7af6d7
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Improve read_verilog debug output capabilities
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-21 20:52:29 +01:00 |
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Eddie Hung
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5597270b9e
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Opt
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2019-03-21 10:20:27 -07:00 |
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Eddie Hung
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2b911e270b
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Fix spacing
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2019-03-20 12:28:39 -07:00 |
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Eddie Hung
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81c207fb9b
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Fine tune cells_map.v
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2019-03-20 10:55:14 -07:00 |
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Eddie Hung
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505e4c2d59
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Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
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2019-03-19 21:58:05 -07:00 |
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Eddie Hung
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5445cd4d00
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Add support for variable length Xilinx SRL > 128
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2019-03-19 17:44:33 -07:00 |
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Eddie Hung
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ae2a625d05
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Restore original synth_xilinx commands
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2019-03-19 16:14:08 -07:00 |
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Eddie Hung
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9156e18f92
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Fix spacing
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2019-03-19 16:12:32 -07:00 |
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Eddie Hung
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4cd8f02973
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shregmap -tech xilinx to delete $shiftx for var length SRL
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2019-03-19 15:05:08 -07:00 |
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Eddie Hung
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f239cb821e
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Fix INIT for variable length SRs that have been bumped up one
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2019-03-19 14:54:43 -07:00 |
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Eddie Hung
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24553326dd
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Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19 13:11:30 -07:00 |
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Eddie Hung
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0ea7eba5f1
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Make output port a non chain user
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2019-03-19 13:08:43 -07:00 |
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Clifford Wolf
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8c0740bcf7
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Merge pull request #885 from YosysHQ/clifford/fix873
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
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2019-03-19 20:31:53 +01:00 |
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Clifford Wolf
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fe1fb1336b
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Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-19 20:30:28 +01:00 |
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Eddie Hung
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a7ac8393d4
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Merge pull request #808 from eddiehung/read_aiger
Add new read_aiger frontend
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2019-03-19 09:41:40 -07:00 |
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Eddie Hung
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02e8dc7ad2
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Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-19 08:52:31 -07:00 |
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Eddie Hung
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3e89cf68bd
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Add author name
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2019-03-19 08:52:06 -07:00 |
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Clifford Wolf
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61f37706f9
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Merge pull request #884 from zachjs/master
fix local name resolution in prefix constructs
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2019-03-19 14:08:57 +01:00 |
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Zachary Snow
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a5f4b83637
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fix local name resolution in prefix constructs
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2019-03-18 20:43:20 -04:00 |
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Eddie Hung
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ed32119d13
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Fix shregmap to correctly recognise non chain users; cleanup
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2019-03-18 16:12:19 -07:00 |
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Eddie Hung
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b94db54664
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shiftx NULL pointer check
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2019-03-18 13:35:54 -07:00 |
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Clifford Wolf
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90bce04156
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Update issue template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-17 12:53:47 +01:00 |
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Clifford Wolf
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6aae502a36
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Update issue template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-17 12:44:23 +01:00 |
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Eddie Hung
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d6d9ef0fee
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Cleanup
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2019-03-16 12:49:46 -07:00 |
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Eddie Hung
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fadeadb8c8
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Only accept <128 for variable length, only if $shiftx exclusive
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2019-03-16 08:51:13 -07:00 |
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Clifford Wolf
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5481205094
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Merge pull request #877 from FelixVi/master
Add note about test requirements in README
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2019-03-16 14:19:02 +01:00 |
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Felix Vietmeyer
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a71c38f163
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Add note about test requirements in README
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2019-03-16 06:20:59 -06:00 |
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Eddie Hung
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29a8d4745e
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Cleanup synth_xilinx
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2019-03-15 23:01:40 -07:00 |
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Eddie Hung
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06f8f2654a
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Working
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2019-03-15 19:13:40 -07:00 |
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Clifford Wolf
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aa65d3fe65
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Improve mix of src/wire/wirebit coverage in "mutate -list"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-16 00:55:46 +01:00 |
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Clifford Wolf
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3fb363ec8c
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Merge pull request #876 from YosysHQ/clifford/fmcombine
Add fmcombine pass
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2019-03-16 00:17:15 +01:00 |
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Clifford Wolf
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dacaebae35
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Add "fmcombine -fwd -bwd -nop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 21:45:37 +01:00 |
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Clifford Wolf
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370db33a4c
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Add fmcombine pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 20:46:17 +01:00 |
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Clifford Wolf
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b5cf8c9442
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Merge pull request #875 from YosysHQ/clifford/mutate
Add "mutate" pass
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2019-03-15 00:51:40 +01:00 |
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Clifford Wolf
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9820ed6531
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Disable realmath tests
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 00:48:23 +01:00 |
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Clifford Wolf
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d1985f6a22
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Improvements in "mutate" list-reduce algorithm
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 00:18:31 +01:00 |
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Clifford Wolf
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27a5d9c91e
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Add "mutate -cfg", improve pick_cover behavior
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 23:20:41 +01:00 |
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Clifford Wolf
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4d304e3da7
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Add a strictly coverage-driven mutation selection strategy
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 23:01:55 +01:00 |
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Clifford Wolf
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2a4263a75d
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Improve "mutate" wire coverage metric
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 23:01:01 +01:00 |
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Clifford Wolf
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1b4fdbb0d8
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Add more mutation types, improve mutation src cover
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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bacca57537
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Fix smtbmc.py handling of zero appended steps
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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6ad5d036c5
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Add "mutate" command DB reduce functionality
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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76c9c350e7
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Add hashlib "<container>::element(int n)" methods
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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8e6b69d7bb
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Add "mutate -mode inv", various other mutate improvements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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ea8ee24140
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Add basic "mutate -list N" framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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c4575103af
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Merge pull request #874 from YosysHQ/clifford/andopt
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
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2019-03-14 21:22:16 +01:00 |
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Clifford Wolf
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f806b95ed6
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Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 20:52:00 +01:00 |
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Clifford Wolf
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44a44a06ed
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Merge pull request #872 from YosysHQ/clifford/pmuxfix
Improve handling of "full_case" attributes
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2019-03-14 18:42:45 +01:00 |
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