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Author	SHA1	Message	Date
Eddie Hung	0318860b93	Add write address to abc_scc_break of ECP5 dist RAM	2019-06-28 09:45:48 -07:00
Eddie Hung	b9ddee0c87	Fix DO4 typo	2019-06-28 09:45:40 -07:00
Eddie Hung	00f63d82ce	Reduce diff with upstream	2019-06-27 16:13:22 -07:00
Eddie Hung	af8a5ae5fe	Extraneous newline	2019-06-27 16:12:20 -07:00
Eddie Hung	4daa746797	Remove noise from ice40/cells_sim.v	2019-06-27 16:11:39 -07:00
Eddie Hung	9398921af1	Refactor for one "abc_carry" attribute on module	2019-06-27 16:07:14 -07:00
Eddie Hung	550760cc72	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-06-27 15:30:00 -07:00
Eddie Hung	a625854ac5	Do not use Module::remove() iterator version	2019-06-27 15:29:20 -07:00
Eddie Hung	312c03e4ca	Remove redundant doc	2019-06-27 15:28:55 -07:00
Eddie Hung	137c91d9a9	Remove &retime when abc9 -fast	2019-06-27 15:17:39 -07:00
Eddie Hung	6bf73e3546	Cleanup abc9.cc	2019-06-27 15:15:56 -07:00
Eddie Hung	fb30fcb7c5	Undo iterator based Module::remove() for cells, as containers will not ... invalidate	2019-06-27 15:03:21 -07:00
Eddie Hung	9a371cfba9	Merge remote-tracking branch 'origin/master' into xaig	2019-06-27 12:53:23 -07:00
Eddie Hung	c4c39e9814	Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog ... tests: Check that Icarus can parse arch sim models	2019-06-27 12:31:15 -07:00
Eddie Hung	440f173aef	Merge remote-tracking branch 'origin/master' into xaig	2019-06-27 11:54:34 -07:00
Eddie Hung	eab8384ec7	Grr	2019-06-27 11:53:42 -07:00
Eddie Hung	36f3cc9dcc	Capitalisation	2019-06-27 11:50:12 -07:00
Eddie Hung	d5cfe341f9	Make CHANGELOG clearer	2019-06-27 11:50:12 -07:00
Eddie Hung	6c210e5813	Merge pull request #1143 from YosysHQ/clifford/fix1135 ... Add "pmux2shiftx -norange"	2019-06-27 11:48:48 -07:00
Eddie Hung	83f143015b	Merge remote-tracking branch 'origin/master' into xaig	2019-06-27 11:31:19 -07:00
Eddie Hung	1237a4c116	Add warning if synth_xilinx -abc9 with family != xc7	2019-06-27 11:22:49 -07:00
Eddie Hung	469f98b6bd	Remove unneeded include	2019-06-27 11:20:40 -07:00
Eddie Hung	6c256b8cda	Merge origin/master	2019-06-27 11:20:15 -07:00
Eddie Hung	ab7c431905	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00
Eddie Hung	18acb72c05	Add #1135 testcase	2019-06-27 11:02:52 -07:00
Eddie Hung	760819e10d	synth_xilinx -arch -> -family, consistent with older synth_intel	2019-06-27 07:24:47 -07:00
Eddie Hung	ee77ee6973	Merge pull request #1142 from YosysHQ/clifford/fix1132 ... Fix handling of partial covers in muxcover	2019-06-27 07:21:31 -07:00
Eddie Hung	bb4ae8bc66	Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux ... synth_xilinx: Add -nocarry and -nowidelut options	2019-06-27 06:04:56 -07:00
Eddie Hung	3910bc2ea6	Copy tests from eddie/fix1132	2019-06-27 06:01:50 -07:00
Clifford Wolf	7c14678ec0	Add "pmux2shiftx -norange", fixes #1135 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-27 10:59:12 +02:00
Clifford Wolf	69d810e4a8	Fix handling of partial covers in muxcover, fixes #1132 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-27 09:42:58 +02:00
Eddie Hung	c226af3f56	Fix spacing	2019-06-26 20:03:34 -07:00
Eddie Hung	080a5ca536	Improve debugging message for comb loops	2019-06-26 20:02:38 -07:00
Eddie Hung	4de25a1949	Add WE to ECP5 dist RAM's abc_scc_break too	2019-06-26 20:02:19 -07:00
Eddie Hung	a7a88109f5	Update comment on boxes	2019-06-26 20:00:15 -07:00
Eddie Hung	b7bef15b16	Add "WE" to dist RAM's abc_scc_break	2019-06-26 19:58:09 -07:00
Eddie Hung	26efd6f0a9	Support more than one port in the abc_scc_break attr	2019-06-26 19:57:54 -07:00
Eddie Hung	1d0be89214	Add write_xaiger into CHANGELOG	2019-06-26 19:17:11 -07:00
Eddie Hung	5fa2afc58c	Merge branch 'koriakin/xc7nocarrymux' into xaig	2019-06-26 10:47:53 -07:00
Eddie Hung	6db181471e	Grrr	2019-06-26 10:47:03 -07:00
David Shah	71b046d639	tests: Check that Icarus can parse arch sim models ... Signed-off-by: David Shah <dave@ds0.me>	2019-06-26 18:46:22 +01:00
Eddie Hung	5e1b8d458b	Remove unused var	2019-06-26 10:33:07 -07:00
Eddie Hung	988e6163ab	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00
Eddie Hung	741ebba70a	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-06-26 10:10:16 -07:00
Eddie Hung	86a5fbcde9	Merge branch 'koriakin/xc7nocarrymux' into xaig	2019-06-26 10:09:59 -07:00
Eddie Hung	138989e1a3	Fix spacing	2019-06-26 10:09:18 -07:00
Eddie Hung	df3a037489	Merge branch 'koriakin/xc7nocarrymux' into xaig	2019-06-26 10:08:40 -07:00
Eddie Hung	cb722e7b58	Oops. Actually use nocarry flag as spotted by @koriakin	2019-06-26 10:06:33 -07:00
Clifford Wolf	0d2b87e3ed	Merge pull request #1137 from mmicko/cell_sim_fix ... Simulation model verilog fix	2019-06-26 19:06:10 +02:00
Eddie Hung	799b18263f	Merge branch 'koriakin/xc7nocarrymux' into xaig	2019-06-26 10:04:01 -07:00