mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-13 20:33:04 +00:00
Code Activity
5948 commits 124 branches 64 tags 45 MiB
Commit graph

5 commits

Author SHA1 Message Date
Eddie Hung
efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Eddie Hung
99a3fee8f4 Add "min bits" and "min wports" to xilinx dram rules 2019-05-23 11:32:28 -07:00
Clifford Wolf
7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf
229825e1b8 Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
Clifford Wolf
b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00