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yosys/techlibs/xilinx/drams.txt
2015-04-09 16:08:54 +02:00

37 lines
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bram $__XILINX_RAM64X1D
init 1
abits 6
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
bram $__XILINX_RAM128X1D
init 1
abits 7
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM64X1D
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
make_outreg
endmatch