1356 commits

Author	SHA1	Message	Date
Akash Levy	469f5a707a	Merge branch 'YosysHQ:main' into main	2024-10-14 11:21:54 -07:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Akash Levy	bf4b7ec0ea	Merge branch 'YosysHQ:main' into main	2024-10-11 15:40:49 -07:00
Martin Povišer	a00137c2f6	Merge pull request #4625 from povik/cellmatch-lut ... cellmatch: Size the `lut` attribute	2024-10-11 14:08:55 +02:00
Akash Levy	fdc4c54c66	Merge branch 'YosysHQ:main' into main	2024-10-07 07:27:27 -10:00
Martin Povišer	9479d3bd3c	Merge pull request #4637 from YosysHQ/emil/bufnorm-warning ... bufnorm: avoid warning. NFC	2024-10-07 18:01:42 +02:00
Emil J. Tywoniak	a76bcdc58f	bufnorm: avoid remove warning. NFC	2024-10-07 17:58:48 +02:00
Martin Povišer	2e587c835f	abc9_exe: Document SC mapping options	2024-10-07 12:03:49 +02:00
Martin Povišer	3b6dcc7bd0	abc9_exe: Remove -genlib option	2024-10-07 12:03:49 +02:00
Martin Povišer	e0a86d5483	abc_new: Start new command for aiger2-based round trip	2024-10-07 12:03:49 +02:00
Martin Povišer	e58a9b6ab6	abc9: Understand ASIC options similar to abc	2024-10-07 12:03:48 +02:00
Akash Levy	654e92e04e	Fix Liberty issue	2024-10-03 04:14:20 -07:00
Akash Levy	dd487ca8a1	Updating Yosys	2024-10-03 01:46:09 -07:00
Martin Povišer	ec42b42bd9	cellmatch: Size the lut attribute	2024-10-02 11:29:54 +02:00
Akash Levy	599cebfca5	Include pmuxtree	2024-09-29 05:31:51 -07:00
Akash Levy	b1383a80cf	Make renaming nicer for bmuxmap -pmux	2024-09-27 00:54:05 -07:00
Akash Levy	9f44ec8aa1	Merge branch 'YosysHQ:main' into main	2024-09-17 15:24:05 -07:00
Martin Povišer	38de01807e	Mark bufnorm experimental	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	80119386c0	Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	8bb70bac8d	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d027ead4b5	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	f4b7ea5fb3	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	32808a0393	Improvements and fixes to "bufnorm" cmd ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d0b5dfa6ef	Add bufnorm pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Akash Levy	210ec6585f	Merge branch 'YosysHQ:main' into main	2024-09-16 06:59:25 -07:00
Emil J. Tywoniak	f193bcf683	clockgate: help string	2024-09-16 14:20:33 +02:00
Emil J. Tywoniak	be7c93ec6d	clockgate: 1-bit const 0	2024-09-16 13:58:27 +02:00
Emil J	a8a92d3469	clockgate: help string ... Co-authored-by: Martin Povišer <povik@cutebit.org>	2024-09-16 13:55:53 +02:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Emil J. Tywoniak	8b464341c2	clockgate: no initvals	2024-09-11 10:24:48 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Akash Levy	4f6a153961	Working tree balance pass	2024-08-27 08:19:17 -07:00
Akash Levy	f707a3b6cd	Merge branch 'YosysHQ:main' into main	2024-08-26 22:37:42 -07:00
Krystine Sherwin	7b47f645d7	Address warnings ... - Setting default values - Fixing mismatched types - Guarding unused var	2024-08-16 04:30:31 +12:00
Akash Levy	34e5bc1129	Merge branch 'YosysHQ:main' into master	2024-08-14 16:56:53 -07:00
Martin Povišer	3057c13a66	Improve libparse encapsulation	2024-08-13 18:47:36 +02:00
Martin Povišer	78382eaa6f	libparse: Adjust whitespace	2024-08-13 18:47:36 +02:00
Akash Levy	aec3df36d1	Make flatten less expressive	2024-07-07 21:46:23 -07:00
Akash Levy	6795c32167	Make scopeinfo not default	2024-06-19 04:05:02 -07:00
Emil J. Tywoniak	e939182e68	cellmatch: add comments	2024-05-03 16:42:41 +02:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to $cellmatch	2024-05-03 16:42:41 +02:00
Martin Povišer	c0e68dcc4d	cellmatch: Add debug print	2024-05-03 16:42:41 +02:00
Martin Povišer	6a9858cdad	cellmatch: Delegate evaluation to ConstEval	2024-05-03 16:42:41 +02:00
Martin Povišer	86e1080f05	cellmatch: New pass	2024-05-03 16:42:41 +02:00
Martin Povišer	6ff4ecb2b4	techmap: Remove techmap_chtype from the result	2024-05-03 13:33:28 +02:00
Martin Povišer	fc82251105	techmap: Support dynamic cell types	2024-05-03 13:33:28 +02:00
Peter Gadfort	a48825a604	add support for using ABCs library merging when providing multiple liberty files	2024-04-12 13:57:29 -04:00
N. Engelhardt	e4f11eb0a0	Merge pull request #4228 from povik/synth-inject ... synth: Introduce `-extra-map` for amending techmap	2024-03-11 14:55:45 +01:00
Roland Coeurjoly	4a2fb18718	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00