127 commits

Author	SHA1	Message	Date
Clifford Wolf	11f7b8a2a1	Added opt_expr support for div/mod by power-of-two	2016-05-29 12:17:36 +02:00
Clifford Wolf	1761d08dd2	Bugfix and improvements in memory_share	2016-04-21 14:22:58 +02:00
Clifford Wolf	0f94902125	Added tests/simple/graphtest.v	2015-11-30 11:41:12 +01:00
Clifford Wolf	7ae3d1b5a9	More bugfixes in handling of parameters in tasks and functions	2015-11-12 13:02:36 +01:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	ddf3e2dc65	Bugfix in memory_dff	2015-10-31 22:01:41 +01:00
Clifford Wolf	ccdbf41be6	Improvements in wreduce	2015-10-31 13:39:30 +01:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	dcf2e24240	Added $meminit support to "memory" command	2015-02-14 12:55:03 +01:00
Clifford Wolf	913c304fe6	Added $meminit test case	2015-02-14 11:26:20 +01:00
Clifford Wolf	694cc01f1d	improvements in muxtree/select_leaves test	2015-01-18 13:24:01 +01:00
Clifford Wolf	f630868bc9	Improvements in opt_muxtree	2015-01-18 12:57:36 +01:00
Clifford Wolf	f9c096eeda	Added support for task and function args in parentheses	2014-10-27 13:21:57 +01:00
Clifford Wolf	cad98bcd89	Added multi-dim memory test (requires iverilog git head)	2014-08-12 10:37:47 +02:00
Clifford Wolf	91dd87e60b	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
Clifford Wolf	0129d41efa	Fixed AST handling of variables declared inside a functions main block	2014-08-05 08:35:51 +02:00
Clifford Wolf	7d98645fe8	Added "make -j{N}" support to "make test"	2014-07-30 19:23:26 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	50f22ff30c	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	964a67ac41	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	3345fa0bab	Little steps in realmath test bench	2014-06-21 21:43:04 +02:00
Clifford Wolf	df76da8fd7	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:49:59 +02:00
Clifford Wolf	398482eced	Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)	2014-06-15 09:39:22 +02:00
Clifford Wolf	a4ec19c25c	Added tests/realmath to "make test"	2014-06-15 09:31:03 +02:00
Clifford Wolf	f3b4a9dd24	Added support for math functions	2014-06-14 13:36:23 +02:00
Clifford Wolf	406f86a91e	Added realexpr.v test case	2014-06-14 12:01:17 +02:00
Clifford Wolf	3af7c69d1e	added tests for new verilog features	2014-06-07 12:26:11 +02:00
Clifford Wolf	c82db39935	Added tests/simple/repwhile.v	2014-06-06 17:47:20 +02:00
Clifford Wolf	a67cd2d4a2	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	994c83db01	Added multiplier test case from eda playground	2013-12-18 13:43:53 +01:00
Clifford Wolf	fbd06a1afc	Added elsif preproc support	2013-12-18 13:41:36 +01:00
Clifford Wolf	921064c200	Added support for macro arguments	2013-12-18 13:21:02 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	a2d053694b	Fix in sincos testbench gen	2013-12-04 09:24:52 +01:00
Clifford Wolf	d1517b7982	Added sincos test case	2013-12-04 09:10:41 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	65ad556f3d	Another name resolution bugfix for generate blocks	2013-11-20 13:57:40 +01:00