1339 commits

Author	SHA1	Message	Date
Eddie Hung	4d6d593fe3	&scorr before &sweep, remove &retime as recommended	2019-06-17 13:32:08 -07:00
Eddie Hung	a474fe937b	Merge branch 'xaig' into xaig_dff	2019-06-17 13:20:19 -07:00
Eddie Hung	63fc879a5f	Copy not move parameters/attributes	2019-06-17 13:19:45 -07:00
Eddie Hung	7dd3a7f161	Merge branch 'xaig' into xaig_dff	2019-06-17 12:58:41 -07:00
Eddie Hung	b45d06d7a3	Fix leak removing cells during ABC integration; also preserve attr	2019-06-17 12:54:24 -07:00
Eddie Hung	5ce672d1c5	Merge remote-tracking branch 'origin/xaig' into xaig_dff	2019-06-17 12:14:55 -07:00
Eddie Hung	7250c57c5a	Re-enable &dc2	2019-06-17 10:28:51 -07:00
Eddie Hung	fb90d8c18c	Cleanup	2019-06-16 09:34:26 -07:00
Eddie Hung	3ed95dae8d	Cleanup	2019-06-15 22:48:16 -07:00
Eddie Hung	416312b9ed	abc9 to recover_init by default	2019-06-15 22:44:45 -07:00
Eddie Hung	2309459605	Do not treat $__ABC_FF_ as a user cell	2019-06-15 19:36:55 -07:00
Eddie Hung	cdfb634977	Cleanup	2019-06-15 18:18:56 -07:00
Eddie Hung	c2f3f116d0	Use $__ABC_FF_ instead of $_FF_	2019-06-15 18:16:14 -07:00
Eddie Hung	a76c8a7ffd	Fix initialisation of flops	2019-06-15 09:46:35 -07:00
Eddie Hung	ac18a76beb	Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues	2019-06-15 09:34:48 -07:00
Eddie Hung	da487c4f31	For now, short $_DFF_[NP]_ from ff_map.v at re-integration	2019-06-15 09:08:18 -07:00
Eddie Hung	2d85725604	Get rid of compiler warnings	2019-06-14 13:07:56 -07:00
Eddie Hung	a632799d5b	Update abc9 -D doc	2019-06-14 12:29:46 -07:00
Eddie Hung	e391fc8e7b	Enable "abc9 -D <num>" for timing-driven synthesis	2019-06-14 12:28:01 -07:00
Eddie Hung	a48b5bfaa5	Further cleanup based on @daveshah1	2019-06-14 12:25:06 -07:00
Eddie Hung	751e640c1d	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-06-14 10:29:16 -07:00
Eddie Hung	a5425a2f7e	Remove extra semicolon	2019-06-14 10:11:34 -07:00
David Shah	9566573054	ecp5: Add abc9 option ... Signed-off-by: David Shah <dave@ds0.me>	2019-06-14 17:15:02 +01:00
Eddie Hung	2c40b66785	Rip out all non FPGA stuff from abc9	2019-06-12 16:53:12 -07:00
Eddie Hung	f81a189fb8	Fix spelling	2019-06-12 16:52:09 -07:00
Eddie Hung	b3faf0246d	Be more precise when connecting during ABC9 re-integration	2019-06-12 16:04:33 -07:00
Eddie Hung	2e7e73f483	Remove hacky wideports_split from abc9	2019-06-12 15:52:49 -07:00
Eddie Hung	d9974b85e7	Fix compile errors when #if 1 for debug	2019-06-12 15:47:39 -07:00
Eddie Hung	8bb67fa67c	Do not call abc9 if no outputs	2019-06-12 10:18:44 -07:00
Eddie Hung	14e870d4c4	More write_xaiger cleanup	2019-06-12 10:00:57 -07:00
Eddie Hung	b21d29598a	Consistency	2019-06-12 09:40:51 -07:00
Eddie Hung	b2c72f74f0	Merge branch 'xc7mux' into xaig	2019-06-12 09:14:27 -07:00
Eddie Hung	afd620fd5f	Typo: wire delay is -W argument	2019-06-12 09:13:53 -07:00
Eddie Hung	2cbcd6224c	Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" ... This reverts commit a138381ac3, reversing changes made to b77c5da769.	2019-06-12 09:05:02 -07:00
Eddie Hung	1e838a8913	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	2019-06-12 08:49:15 -07:00
Eddie Hung	4c9fde87d1	Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" ... This reverts commit 2dffa4685b.	2019-06-12 08:48:45 -07:00
Eddie Hung	2dffa4685b	Add "-W' wire delay arg to abc9, use from synth_xilinx	2019-06-11 17:10:47 -07:00
Eddie Hung	6cdea93724	Revert "Try way that doesn't involve creating a new wire" ... This reverts commit 2f427acc9e.	2019-06-11 16:05:42 -07:00
Eddie Hung	d26646051c	Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" ... This reverts commit 5174082208, reversing changes made to 54379f9872.	2019-06-11 16:05:27 -07:00
Eddie Hung	5174082208	Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux	2019-06-11 15:48:41 -07:00
Eddie Hung	2f427acc9e	Try way that doesn't involve creating a new wire	2019-06-11 15:48:20 -07:00
Eddie Hung	a138381ac3	Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux	2019-06-10 16:21:43 -07:00
Eddie Hung	f19aa8d989	If d_bit already in sigbit_chain_next, create extra wire	2019-06-10 16:16:40 -07:00
Eddie Hung	a1d4ae78a0	Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" ... This reverts commit 94a5f4e609.	2019-06-10 14:34:43 -07:00
Eddie Hung	7d27e1e431	Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" ... This reverts commit 45d1bdf83a.	2019-06-10 14:34:16 -07:00
Eddie Hung	3579d68193	Revert "Refactor to ShregmapTechXilinx7Static" ... This reverts commit e1e37db860.	2019-06-10 14:34:15 -07:00
Eddie Hung	b6a39351f4	Revert "Add -tech xilinx_static" ... This reverts commit dfe9d95579.	2019-06-10 14:34:14 -07:00
Eddie Hung	e1dbeb3004	Revert "Continue support for ShregmapTechXilinx7Static" ... This reverts commit 72eda94a66.	2019-06-10 14:34:14 -07:00
Eddie Hung	9d8563178e	Revert "shregmap -tech xilinx_static to handle INIT" ... This reverts commit 935df3569b.	2019-06-10 14:34:12 -07:00
Eddie Hung	5a46a0b385	Fine tune aigerparse	2019-06-07 16:57:32 -07:00