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1405 commits

Author SHA1 Message Date
Emil J. Tywoniak 4d96cbec75 clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
Emil J. Tywoniak 983c54c75f clockgate: help string add -dont_use and -liberty 2024-11-18 13:57:49 +01:00
Emil J. Tywoniak a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak e6793da9a0 clockgate: refactor 2024-11-18 12:50:25 +01:00
Emil J. Tywoniak 45880ea7f2 clockgate: add -liberty 2024-11-14 20:37:59 +01:00
Lofty 4f40187759 dfflibmap: move expression code into libparse 2024-11-13 16:06:57 +00:00
Lofty 08ed2c765e dfflibmap: enable inference 2024-11-13 15:57:45 +00:00
Martin Povišer 9da7341003
Merge pull request #4727 from georgerennie/george/bufnorm_constants2 
bufnorm: preserve constant bits when mapping back to connections
 2024-11-13 14:32:15 +01:00
Emil J. Tywoniak 49e1597ea4 filterlib: preserve value quotes 2024-11-12 01:21:07 +01:00
George Rennie ff6c9446c0 bufnorm: preserve constant bits when mapping back to connections 2024-11-12 01:05:15 +01:00
George Rennie 8f6058a7d6 bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
Martin Povišer cbe73c9047 cellmatch: Visit whiteboxes for -derive_luts 2024-11-04 14:28:46 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename -lut_attrs to -derive_luts; document option 2024-11-04 14:28:40 +01:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Martin Povišer a00137c2f6
Merge pull request #4625 from povik/cellmatch-lut 
cellmatch: Size the `lut` attribute
 2024-10-11 14:08:55 +02:00
Martin Povišer 9479d3bd3c
Merge pull request #4637 from YosysHQ/emil/bufnorm-warning 
bufnorm: avoid warning. NFC
 2024-10-07 18:01:42 +02:00
Emil J. Tywoniak a76bcdc58f bufnorm: avoid remove warning. NFC 2024-10-07 17:58:48 +02:00
Martin Povišer 2e587c835f abc9_exe: Document SC mapping options 2024-10-07 12:03:49 +02:00
Martin Povišer 3b6dcc7bd0 abc9_exe: Remove -genlib option 2024-10-07 12:03:49 +02:00
Martin Povišer e0a86d5483 abc_new: Start new command for aiger2-based round trip 2024-10-07 12:03:49 +02:00
Martin Povišer e58a9b6ab6 abc9: Understand ASIC options similar to abc 2024-10-07 12:03:48 +02:00
Martin Povišer ec42b42bd9 cellmatch: Size the lut attribute 2024-10-02 11:29:54 +02:00
Martin Povišer 38de01807e Mark bufnorm experimental 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Emil J. Tywoniak f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Emil J. Tywoniak 8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
Emil J. Tywoniak 7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Krystine Sherwin 7b47f645d7
Address warnings 
- Setting default values
- Fixing mismatched types
- Guarding unused var
 2024-08-16 04:30:31 +12:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer 78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
Emil J. Tywoniak e939182e68 cellmatch: add comments 2024-05-03 16:42:41 +02:00
Martin Povišer b143e5678f cellmatch: Rename the special design to $cellmatch 2024-05-03 16:42:41 +02:00
Martin Povišer c0e68dcc4d cellmatch: Add debug print 2024-05-03 16:42:41 +02:00
Martin Povišer 6a9858cdad cellmatch: Delegate evaluation to ConstEval 2024-05-03 16:42:41 +02:00
Martin Povišer 86e1080f05 cellmatch: New pass 2024-05-03 16:42:41 +02:00
Martin Povišer 6ff4ecb2b4 techmap: Remove techmap_chtype from the result 2024-05-03 13:33:28 +02:00
Martin Povišer fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
Peter Gadfort a48825a604 add support for using ABCs library merging when providing multiple liberty files 2024-04-12 13:57:29 -04:00
N. Engelhardt e4f11eb0a0
Merge pull request #4228 from povik/synth-inject 
synth: Introduce `-extra-map` for amending techmap
 2024-03-11 14:55:45 +01:00
Roland Coeurjoly 4a2fb18718 Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc 2024-02-25 17:23:56 +01:00
Roland Coeurjoly 033fa10307 We use CXX instead of LD for linking yosys-filterlib 2024-02-25 16:49:28 +01:00
Martin Povišer 53ca7b48f8 techmap: Fix help message wording 2024-02-22 22:00:56 +01:00
Austin Rovinski 03cadf6474 dfflibmap: use patmatch() from kernel/yosys.cc 
Replace OS matching functions with yosys kernel function

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-20 11:04:55 -05:00
Austin Rovinski 5059bb1d4f dfflibmap: force PathMatchSpecA on WIN32 
Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or
LPCWSTR argument. char* is only convertable to LPCSTR, so use that
implementation

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-19 14:40:46 -05:00
Austin Rovinski 689feed012 dfflibmap: Add a -dont_use flag to ignore cells 
This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-19 13:00:18 -05:00
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Martin Povišer af1a5cfeb9 Address SigBit/SigSpec confusion issues under c++20 2024-02-08 17:48:36 +01:00
Jannis Harder 8902fc94b6 Suport $scopeinfo in flatten and opt_clean 2024-02-06 17:51:29 +01:00
Martin Povišer d6566eb344 booth: Redo baseline architecture summation 
Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
 2023-11-22 15:47:11 +01:00
Martin Povišer beb5cb55a5 booth: Expose -lowpower option 2023-11-22 15:29:59 +01:00
Martin Povišer 7005ea9411 booth: Revisit help 2023-11-22 15:29:59 +01:00
Martin Povišer 48b73be8c6 booth: Replace the default signed architecture 
Generalize what was formerly the unsigned-only architecture to support
both signed and unsigned multiplication, use that as default, and set
aside the special low-power architecture that was formerly used for
signed multipliers.
 2023-11-22 15:29:59 +01:00
Martin Povišer f50894d8bf booth: Drop extra decoder arguments 2023-11-22 15:29:54 +01:00
Martin Povišer 579f6bdc17 booth: Do not special-case bottom rows 
Later on all the rows are cropped to the target size anyway, so there's
no harm in transitionally including extra top bits.
 2023-11-22 15:12:15 +01:00
Martin Povišer da207cdce0 booth: Make less assumptions when aligning partial products 2023-11-22 15:12:15 +01:00
Martin Povišer 69e994ff75 booth: Clean unused FA index variable 2023-11-22 12:47:09 +01:00
Martin Povišer d8408b2350 booth: Move up signed quadrant 1 logic 2023-11-22 12:46:15 +01:00
Martin Povišer 8d33cc2fb6 booth: Refactor signed CPA 2023-11-22 12:46:15 +01:00
Martin Povišer 00e899f98d booth: Refactor signed multiplier full adders emission 2023-11-22 12:46:15 +01:00
Lofty d21c464ae4
Merge pull request #3946 from rmlarsen/toposort 
Speed up TopoSort by 2.7-3.3x.
 2023-10-17 13:00:18 +01:00
Rasmus Munk Larsen 0a37c2a301 Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten. 
Add back statement that inserts nodes in order in opt_expr.cc.
 2023-10-05 17:01:42 -07:00
Martin Povišer 0434f9d3d1 booth: Fix vacancy check when summing down result 
In commit fedd12261 ("booth: Move away from explicit `Wire` pointers")
a bug was introduced when checking for vacant slots in arrays holding
some intermediate results. Non-wire SigBit values were taken to imply
a vacant slot, but actually a constant one can make its way into those
results, if the multiplier cell configuration is just right. Fix the
vacancy check to address the bug.
 2023-10-04 23:21:40 +02:00
Rasmus Munk Larsen 1bbc12f389 Revert changes to techmap.cc. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen 67f1700486 Revert formatting changes. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen abd9c51963 Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959 2023-10-02 17:32:56 +01:00
Martin Povišer 6b70b3dbef booth: Fix assertion 
Fix assertion to what it should be per Andy's comments.
 2023-09-28 11:50:57 +02:00
Martin Povišer 91bcf81dbd booth: Note down debug prints are broken 2023-09-25 14:51:26 +02:00
Martin Povišer 7179e4f4b8 booth: Improve user interface 2023-09-25 14:50:41 +02:00
Martin Povišer cde2a0b926 booth: Make more use of appropriate helpers 
Use the `addFa` helper, do not misuse `new_id` and make other changes
to the transformation code.
 2023-09-25 14:50:41 +02:00
Martin Povišer 62302f601d booth: Remove more of unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer 30f8387b75 booth: Rewrite the main cell selection loop 2023-09-25 14:50:41 +02:00
Martin Povišer 986507f95f booth: Streamline the low-level circuit emission 
For the basic single-bit operations, opt for gate cells (`$_AND_` etc.)
instead of the coarse cells (`$and` etc.). For the emission of cells
move to the conventional module methods (`module->addAndGate`) away
from the local helpers. While at it, touch on the surrounding code.
 2023-09-25 14:50:41 +02:00
Martin Povišer cb05262fc4 booth: Remove now-unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer fedd12261f booth: Move away from explicit Wire pointers 
To represent intermediate signals use the `SigBit`/`SigSpec` classes as
is customary in the Yosys codebase. Do not pass around `Wire` pointers
unless we have special reason to.
 2023-09-25 14:50:41 +02:00
Rasmus Munk Larsen e0042bdff7 Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. 2023-09-20 15:49:05 -07:00
Martin Povišer 54be4aca90
Merge pull request #3924 from andyfox-rushc/master 
multpass -- create Booth Encoded multipliers for
 2023-09-18 16:46:59 +02:00
Miodrag Milanović 88ce47e4f0
Merge pull request #3892 from QuantamHD/dont_use 
abc: Exposes dont_use flag in ABC
 2023-09-12 14:58:44 +02:00
andyfox-rushc e4fe522767 MultPassWorker -> BoothPassWorker 2023-09-11 13:00:11 -07:00
andyfox-rushc eccc0ae6db Based passes/techmap/Makefile.inc changes on latest in yosys 2023-09-11 12:14:12 -07:00
andyfox-rushc a2c8e47295 multpass.cc -> booth.cc, added author/support contact info 2023-09-11 11:39:13 -07:00
andyfox-rushc 1b5287af59 cpa_carry array added to heap 2023-09-10 14:20:30 -07:00
andyfox-rushc 8d4b6c2f69 Switched arrays for signed multiplier construction to heap 2023-09-10 13:31:47 -07:00
andyfox-rushc d77fb81507 2d array -> 1d array in module generator 2023-09-10 12:45:36 -07:00
andyfox-rushc 6d29dc659b renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script 2023-09-08 15:34:56 -07:00
andyfox-rushc 411acc4a0a Fixed edge size cases for signed/unsigned booth generator 2023-09-08 13:41:31 -07:00
andyfox-rushc fedefa26bc multpass -- create Booth Encoded multipliers for 2023-09-06 16:35:17 -07:00
Martin Povišer e995dddeaa abc: Warn about replacing undef bits 2023-09-05 10:45:30 +02:00
Ethan Mahintorabi d525a41497
abc: Exposes dont_use flag in ABC 
ABC's read_lib command has a dont_use
cell list that is configurable by the user.

This PR exposes that option to Yosys.

See
5405d4787a/src/map/scl/scl.c (L285)
for documentation on this option.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-08-15 20:03:46 +00:00
N. Engelhardt 43780c9812
Merge pull request #3838 from povik/various-cleanup 2023-07-24 16:24:23 +02:00
Catherine 6965abeefa abc, abc9_exe: fix build on WASI (and others with const* stdout). 
C does not guarantee that stdout/stderr can be reassigned.
Most platforms do make them assignable, however musl and WASI that
is based on musl do not. WASI does not have `dup2()`; instead it has
its own non-portable version of it that can only assign to previously
allocated fds.

Update the stream redirection code so that it does the right thing
on WASI and other platforms.
 2023-07-23 05:13:29 +01:00
Catherine 411b6e98cd abc, abc9_exe: respect -q when built with linked ABC. 
This is mostly important for YoWASP builds, since those do not have
a way to build with external ABC (I prototyped it but for some reason
ABC always segfaults when built as an independent Wasm binary...)
 2023-07-23 02:03:29 +01:00