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Author SHA1 Message Date
Krystine Sherwin 7343ef159e
synth_quicklogic: Testing double_sync_ram_tdp 2023-12-04 11:17:18 +13:00
Krystine Sherwin 945e78e266
Adding double_sync_ram_tdp to blockram.v 2023-12-04 11:16:50 +13:00
Krystine Sherwin 2d6738bb10
qlf_tests: minor adjustment 
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
 2023-12-04 09:38:48 +13:00
N. Engelhardt 1bd3678f75 remove example test 2023-12-01 14:28:50 +01:00
N. Engelhardt c2fc33f0eb fix test setup for synth_quicklogic memory tests 2023-12-01 14:03:07 +01:00
N. Engelhardt 190cbd54b1 fix test setup for synth_quicklogic memory tests 2023-12-01 10:47:39 +01:00
Krystine Sherwin 5634d98ccb
attempting to sim split memory tests 
and failing
 2023-12-01 21:16:58 +13:00
Krystine Sherwin d9d54e66c7
QLF_TDP36K: asymmetric simulation tests 2023-12-01 20:47:39 +13:00
Krystine Sherwin 0cd4a10c81
QLF_TDP36K: truncation tests matter 
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
 2023-12-01 17:14:01 +13:00
Krystine Sherwin 7f90fafd15
QLF_TDP36K: more basic tdp/sdp sim tests 
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
 2023-12-01 17:00:15 +13:00
Krystine Sherwin 7a659bdd26
QLF_TDP36K: parameterised sim test gen 
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
 2023-12-01 16:26:00 +13:00
Krystine Sherwin b62173775c
QLF_TDP36K: test bram_tdp post synth 2023-12-01 09:52:27 +13:00
N. Engelhardt 64609afe2c add example memory test 2023-11-30 19:35:43 +01:00
Krystine Sherwin f810bd88f5 quicklogic: wildcard asymmetric memory tests 2023-11-30 17:33:13 +01:00
Krystine Sherwin c54d6b29d3 tests: asymmetric sync rams now correctly asymmetric 
Also both use the same named parameters for better mirroring.
 2023-11-30 17:33:13 +01:00
Krystine Sherwin cdb20baf1f quicklogic: testing port widths on split rams 2023-11-30 17:33:13 +01:00
Krystine Sherwin 4c03c84fa7 quicklogic: testing 1:4 assymetric memory 2023-11-30 17:33:13 +01:00
Krystine Sherwin a1073c706e quicklogic: fix double width read 2023-11-30 17:33:13 +01:00
Krystine Sherwin fbf8607b97 quicklogic: Testing split TDP36K 
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
 2023-11-30 17:33:13 +01:00
Krystine Sherwin 0cd67ce473 quicklogic: Initial blockram tests 
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
 2023-11-30 17:33:13 +01:00
Martin Povišer fb34167fd4 fixup! quicklogic: Add basic k6n10f tests 2023-11-30 13:43:56 +01:00
Martin Povišer d11a85fcba fixup! quicklogic: Add basic k6n10f tests 2023-11-30 11:12:55 +01:00
Martin Povišer 193144e68b fixup! quicklogic: Add basic k6n10f tests 2023-11-30 10:45:39 +01:00
Martin Povišer 49cee23128 quicklogic: Add RAM_INIT to specialized BRAM models 2023-11-30 10:41:55 +01:00
Martin Povišer a47c2aaa97 fixup! quicklogic: Add missing RAM_INIT param on TDP36K sim model 2023-11-30 10:18:48 +01:00
Martin Povišer e70122b74e fixup! quicklogic: Add basic k6n10f tests 2023-11-29 11:20:16 +01:00
Martin Povišer 6066115d5b quicklogic: Add missing RAM_INIT param on TDP36K sim model 2023-11-29 11:04:34 +01:00
Martin Povišer 04d2f55bec fixup! add qlf_k6n10f architecture + bram inference 2023-11-27 18:28:10 +01:00
Martin Povišer 53bda484f8 quicklogic: Set initial values on inferred TDP36K 2023-11-27 17:43:21 +01:00
Martin Povišer 5bc587c843 quicklogic: Add k6n10f DSP test 2023-11-27 17:43:21 +01:00
Martin Povišer 03b45c883a ql_dsp_io_regs: Fix ID strings, constant detection 2023-11-27 17:27:46 +01:00
Martin Povišer 502559cba4 quicklogic: Fix dffs.ys test 2023-11-27 17:27:46 +01:00
Martin Povišer 9d04201e86 synth_quicklogic: Fix missing FF mapping 2023-11-27 14:22:28 +01:00
Martin Povišer 3e004f7b13 quicklogic: Drop blackbox off adder_carry 2023-11-27 14:21:59 +01:00
Martin Povišer a3b3333eeb quicklogic: Add basic k6n10f tests 2023-11-27 12:14:48 +01:00
Martin Povišer 90f427c7a8 synth_quiclogic: Fix conditioning of bram passes 2023-11-27 12:05:55 +01:00
Martin Povišer 74296e3d92 quicklogic: Move pp3 tests one level down 2023-11-27 12:05:55 +01:00
Martin Povišer f84ab98055 ql_dsp_macc: Tune DSP inference code 2023-11-27 12:05:55 +01:00
Martin Povišer 306e688406 ql_dsp_*: Clean up 
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
 2023-11-27 12:05:55 +01:00
Martin Povišer 6d7dafe5e5 ql_k6n10f: Remove support for parameter-configured DSP variety 2023-11-27 12:05:55 +01:00
N. Engelhardt a19ac1bbe1 merge brams_final_map.v into brams_map.v 2023-11-27 12:05:55 +01:00
N. Engelhardt 9ce53ea3e2 add dsp inference 2023-11-27 12:05:53 +01:00
N. Engelhardt 7c0dbc8822 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-11-27 12:05:52 +01:00
N. Engelhardt 688455ef69 add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-11-27 12:05:45 +01:00
N. Engelhardt e230a871be synth_quicklogic: rearrange files to prepare for adding more architectures 2023-11-27 08:37:33 +01:00
github-actions[bot] 031ad38b5c Bump version 2023-11-24 00:15:38 +00:00
Miodrag Milanović 5e603c2241
Merge pull request #4042 from YosysHQ/verific_cell 
Verific: Add attributes to module instantiation
 2023-11-23 11:38:01 +01:00
Miodrag Milanovic 8f207eed1b Add attributes to module instantiation 2023-11-23 11:01:49 +01:00
github-actions[bot] c95298225d Bump version 2023-11-21 00:16:08 +00:00
Martin Povišer 34f851f132
Merge pull request #4040 from povik/fmt-time 
fmt: Handle free-standing time arguments
 2023-11-20 18:11:24 +01:00