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Code Activity
12782 commits 94 branches 53 tags 45 MiB
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8 commits

Author SHA1 Message Date
N. Engelhardt
64609afe2c add example memory test 2023-11-30 19:35:43 +01:00
N. Engelhardt
a19ac1bbe1 merge brams_final_map.v into brams_map.v 2023-11-27 12:05:55 +01:00
N. Engelhardt
9ce53ea3e2 add dsp inference 2023-11-27 12:05:53 +01:00
N. Engelhardt
7c0dbc8822 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-11-27 12:05:52 +01:00
N. Engelhardt
688455ef69 add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-11-27 12:05:45 +01:00
N. Engelhardt
e230a871be synth_quicklogic: rearrange files to prepare for adding more architectures 2023-11-27 08:37:33 +01:00
Lofty
dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Lofty
f4298b057a quicklogic: PolarPro 3 support 
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
 2021-03-18 13:28:16 +01:00