mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 16:45:32 +00:00
Code Activity
14752 commits 93 branches 53 tags 44 MiB
Commit graph

51 commits

Author SHA1 Message Date
Miodrag Milanovic
b76c72056b set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
Miodrag Milanovic
545a3417c8 resetall does not affect text defines, but undefineall does 2022-08-10 11:38:50 +02:00
Thomas Sailer
4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers 
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
 2021-12-15 18:06:02 -07:00
Zachary Snow
3156226233 verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
0505c604e7 preproc: Fix up conditional handling. 
Fixes #2710.
Fixes #2711.
 2021-03-30 02:29:26 +02:00
Zachary Snow
1ec5994100 verilog: fix handling of nested ifdef directives 
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
 2021-03-01 12:28:33 -05:00
Zachary Snow
220cb1f7bb verilog: error on macro invocations with missing argument lists 
This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
 2021-02-19 09:18:41 -05:00
Zachary Snow
27257a419f verilog: strip leading and trailing spaces in macro args 2021-01-28 11:26:35 -05:00
Zachary Snow
4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
georgerennie
c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
Anonymous Maarten
504f220619 MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
Rupert Swarbrick
044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Rodrigo Alejandro Melo
e9dc2759c4 Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
Clifford Wolf
65f197e28f Add check for valid macro names in macro definitions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-07 13:30:03 +01:00
Jim Paris
4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris
872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf
a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
William D. Jones
abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
Clifford Wolf
2c04d883b1 Minor coding style fix 2017-09-26 13:50:14 +02:00
combinatorylogic
64ca0be971 Adding support for string macros and macros with arguments after include 2017-09-21 18:25:02 +01:00
Clifford Wolf
f0db8ffdbc Add support for `resetall compiler directive 2017-04-26 16:09:41 +02:00
Clifford Wolf
088f9c9cab Fix verilog pre-processor for multi-level relative includes 2017-03-14 17:30:20 +01:00
Clifford Wolf
ecdc22b06c Added support for macros as include file names 2016-11-28 14:50:17 +01:00
Clifford Wolf
a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf
f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
ef151b0b30 Fixed handling of "//" in filenames in verilog pre-processor 2015-02-14 08:41:03 +01:00
Clifford Wolf
1bd67d792e Define YOSYS and SYNTHESIS in preproc 2015-01-02 17:11:54 +01:00
Clifford Wolf
c5eb5e56b8 Re-introduced Yosys::readsome() helper function 
(f.read() + f.gcount() made problems with lines > 16kB)
 2014-10-23 10:58:36 +02:00
Clifford Wolf
c3e9922b5d Replaced readsome() with read() and gcount() 2014-10-15 01:12:53 +02:00
Clifford Wolf
8263f6a74a Fixed win32 troubles with f.readsome() 2014-10-11 11:36:22 +02:00
Clifford Wolf
bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf
19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf
6d56172c0d Fixed line numbers when using here-doc macros 2014-08-14 22:26:30 +02:00
Clifford Wolf
f53984795d Added support for non-standard """ macro bodies 2014-08-13 13:03:38 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
7daad40ca4 Fixed counting verilog line numbers for "// synopsys translate_off" sections 2014-07-30 20:18:48 +02:00
Clifford Wolf
e605af8a49 Fixed Verilog pre-processor for files with no trailing newline 2014-07-29 20:14:25 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
02e6f2c5be Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
Clifford Wolf
13359d65ba Fixed parsing of verilog macros at end of line 2014-01-18 19:22:20 +01:00
Clifford Wolf
1dcbba1abf Fixed parsing of non-arg macro calls followed by "(" 2013-12-27 16:25:27 +01:00
Clifford Wolf
72026a934e Fixed parsing of macros with no arguments and expansion text starting with "(" 2013-12-27 15:05:52 +01:00
Clifford Wolf
fbd06a1afc Added elsif preproc support 2013-12-18 13:41:36 +01:00
Clifford Wolf
921064c200 Added support for macro arguments 2013-12-18 13:21:02 +01:00
Clifford Wolf
a362fd81ae Fixed O(n^2) performance bug in verilog preprocessor 2013-11-22 14:08:43 +01:00
Clifford Wolf
e4429c480e Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) 2013-11-22 12:46:02 +01:00
Johann Glaser
a99c224157 Added support for include directories with the new '-I' argument of the 
'read_verilog' command
 2013-08-20 15:48:16 +02:00
Johann Glaser
10a195c0a1 added option '-Dname[=definition]' to command 'read_verilog' 2013-05-19 17:07:52 +02:00