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608 commits

Author SHA1 Message Date
Aman Goel
8b9a8c7f91 Minor correction
Minor typo error correction in -expose with setundef
2018-05-14 18:58:49 -04:00
Aman Goel
b4a303a1b7 Corrections to option -expose in setundef pass 2018-05-13 20:13:54 -04:00
Aman Goel
9286acb687 Add option -expose to setundef pass
Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
2018-05-13 16:53:35 -04:00
Clifford Wolf
0fad1570b5 Some cleanups in setundef.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-13 16:36:12 +02:00
Christian Krämer
c1ecb1b2f1 Add "#ifdef __FreeBSD__"
(Re-commit e3575a8 with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26 Revert "Add "#ifdef __FreeBSD__""
This reverts commit e3575a86c5.
2018-05-13 13:06:36 +02:00
Johnny Sorocil
e3575a86c5 Add "#ifdef __FreeBSD__" 2018-05-05 13:02:44 +02:00
Clifford Wolf
83ffb23739 Add "setundef -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:35 +01:00
Clifford Wolf
61a9e2eeb3 Fix connwrappers help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:54:34 +01:00
Clifford Wolf
717abc93a8 Recognize stand-alone obj pattern even when it contains a slash 2018-02-13 14:55:24 +01:00
Clifford Wolf
a96c775a73 Add support for "yosys -E"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf
4f31cb6dad Add "ltp" command 2017-10-31 12:40:25 +01:00
Clifford Wolf
3f22f48eeb Add blackbox command 2017-10-04 18:30:42 +02:00
Clifford Wolf
d38a64b1cf More intuitive handling of "cd .." for singleton modules 2017-08-19 00:15:12 +02:00
Clifford Wolf
c00d8a5b73 Add $alu to list of supported cells for "stat -width" 2017-07-14 11:32:49 +02:00
Clifford Wolf
0f217080cf Add "design -import" 2017-06-30 19:18:52 +02:00
Clifford Wolf
8952bd6f45 Add chtype command 2017-06-30 17:57:34 +02:00
Clifford Wolf
05df3dbee4 Add "setundef -anyseq" 2017-05-28 11:59:05 +02:00
Clifford Wolf
9ed4c9d710 Improve write_aiger handling of unconnected nets and constants 2017-05-28 11:31:35 +02:00
Clifford Wolf
dee4ec1661 Fix gcc compiler warning 2017-04-05 11:21:06 +02:00
Clifford Wolf
1a6c02a532 Add "chformal -assert2assume" and friends 2017-02-28 00:00:44 +01:00
Clifford Wolf
db7fc0e32d Add "chformal" pass 2017-02-27 13:25:28 +01:00
Clifford Wolf
0cac95ea94 Added "check -initdrv" 2017-01-04 18:12:41 +01:00
Clifford Wolf
b1cdf772eb Added "design -reset-vlog" 2016-11-30 11:25:55 +01:00
Clifford Wolf
e444e59963 Added wire start_offset and upto handling to splitnets cmd 2016-11-23 13:54:33 +01:00
Clifford Wolf
97ac77513f Bugfix in "setundef" pass 2016-11-08 18:53:36 +01:00
Clifford Wolf
ef603c6fe1 Implemented "scc -set_attr" 2016-11-06 00:04:10 +01:00
Clifford Wolf
914aa8a5d3 Bugfix in "scc" command 2016-11-06 00:03:35 +01:00
Clifford Wolf
3655d7fea7 Added "setparam -type" 2016-10-19 13:54:04 +02:00
Clifford Wolf
f3f5a02045 Added "tee +INT -INT" 2016-09-06 17:43:24 +02:00
Clifford Wolf
66582964bc Improved "show" help message 2016-08-28 12:34:36 +02:00
Clifford Wolf
321e15b0bf Minor fixes in show command 2016-08-16 00:36:24 +02:00
Clifford Wolf
6ed6b3cb6d Replaced "select -assert-limit" with -assert-max and -assert-min 2016-07-01 12:24:13 +02:00
eshellko
9a742f4069 Added 'assert-limit' option for 'select' command
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
2016-07-01 10:24:22 +04:00
Clifford Wolf
dcf576641b Added "setundef -init" 2016-06-03 11:38:31 +02:00
Clifford Wolf
611f121cb9 Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop 2016-05-27 16:33:13 +02:00
Clifford Wolf
e01464e2ac Added "qwp -v" 2016-04-28 23:17:30 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
a47f69536a Added support for installed plugins 2016-03-30 10:02:03 +02:00
Clifford Wolf
2c7e107d7a Support for abstract modules in chparam 2016-03-21 16:37:35 +01:00
Clifford Wolf
825b99efc1 Added "stat -liberty" for calculating chip area 2016-02-04 12:26:13 +01:00
Clifford Wolf
1d62f8710f Fixed "splitnets -ports" for hierarchical designs 2015-12-22 13:25:00 +01:00
Clifford Wolf
ab0c44d3ed Added %R select expression 2015-12-20 13:35:58 +01:00
Clifford Wolf
e61c7f887a Added torder command 2015-11-19 15:34:32 +01:00
Clifford Wolf
207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf
7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf
6af8076967 improvement in "stat" 2015-10-24 21:56:53 +02:00
Clifford Wolf
c35db8c19e Disabled "Skipping blackbox module" msg in show command 2015-10-23 20:11:05 +02:00
Clifford Wolf
c58bd5dc30 Added edgetypes command 2015-09-27 11:53:20 +02:00