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Code Activity
13655 commits 93 branches 53 tags 44 MiB
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1430 commits

Author SHA1 Message Date
Clifford Wolf
d9bb5f3637 Add ENABLE_GLOB Makefile switch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-11 01:08:36 -07:00
Eddie Hung
f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Eddie Hung
3ea0161ae7 Add IdString::ends_with() 2019-02-26 12:04:16 -08:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd 
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
 2019-02-22 06:55:48 +01:00
Eddie Hung
a8803a1519 Merge remote-tracking branch 'origin/master' into xaig 2019-02-21 11:23:00 -08:00
Clifford Wolf
0a6588569b Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 15:51:59 +01:00
Clifford Wolf
953e0bf88d Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 14:27:46 +01:00
Clifford Wolf
246391200e Add FF support to wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:36:42 +01:00
Eddie Hung
edf7267019 Refactor kernel/cost.h definition into cost.cc 2019-02-08 13:58:20 -08:00
Clifford Wolf
e70ebe557c Add optional nullstr argument to log_id() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:06:48 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark
18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
whitequark
2ca237e086 tcl: add support for passing arguments to scripts. 2018-12-20 07:32:24 +00:00
Clifford Wolf
e90195b737 Improve ConstEval error handling for non-eval cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-29 05:07:40 +01:00
Jon Burgess
6732e56632 Avoid assert when label is an empty string 
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.

802             if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
 2018-10-28 14:57:04 +00:00
whentze
9ed77f5ba8 fix unhandled std::out_of_range when calling yosys with 3-character argument 2018-10-22 19:40:22 +02:00
Ruben Undheim
c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Adrian Wheeldon
1355492c89 Fix IdString M in setup_stdcells() 2018-10-04 15:36:26 +01:00
Benedikt Tutzer
6f8abc1143 Exposed generator script to make-process 2018-09-19 10:32:34 +02:00
Miodrag Milanovic
c5e9034834 Fix Cygwin build and document needed packages 2018-09-19 10:16:53 +02:00
Benedikt Tutzer
604734b484 added functions whose definitions are split over multiple lines 2018-08-23 14:48:20 +02:00
Benedikt Tutzer
586d7df7e2 added default yosys license text 2018-08-23 14:39:44 +02:00
Benedikt Tutzer
ba18e0f81a Fixed segfault / multiple free issue with lists 2018-08-23 13:57:37 +02:00
Benedikt Tutzer
0ecfffa69c Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function 2018-08-22 14:42:42 +02:00
Benedikt Tutzer
60608a86bb Fixed Identation 2018-08-22 11:59:22 +02:00
Benedikt Tutzer
038caab4e0 Wrapped functions that use unsigned int or type_t as types 2018-08-21 15:25:43 +02:00
Benedikt Tutzer
4acb29db0c added operators <, == and != 2018-08-21 14:49:35 +02:00
Benedikt Tutzer
334bfce4c4 Added previousely missed functions 2018-08-21 13:15:08 +02:00
Benedikt Tutzer
29efc9d0b1 Deleted duplicate Destructor 2018-08-21 11:07:59 +02:00
Benedikt Tutzer
95d65971f3 added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile 2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d41c68ee5a The share directory cannot be searched when used as a Python library, only in shell mode 2018-08-20 15:27:50 +02:00
Benedikt Tutzer
6d18837d62 Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path 2018-08-20 15:11:06 +02:00
Benedikt Tutzer
5864db3c2b Fixed issue when using a python plugin in the yosys shell 2018-08-20 14:44:03 +02:00
Benedikt Tutzer
d79a2808cf Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script 2018-08-16 16:00:11 +02:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
litghost
80d7e007ff Map .eblif extension as blif. 
Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
 2018-08-13 14:02:53 -07:00
Benedikt Tutzer
bf7b73acfc Added Wrappers for: 
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
 2018-08-13 15:18:46 +02:00
Benedikt Tutzer
416946a16a Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more 2018-08-01 10:57:57 +02:00
Benedikt Tutzer
79d7e608cf Setup is called automatically when the module is loaded, shutdown when python exits 2018-08-01 10:57:46 +02:00
Benedikt Tutzer
57d2197703 Cleaned up comments 2018-08-01 10:57:41 +02:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller
1a60126a34 Provide source-location logging. 
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
 2018-07-19 10:22:02 -07:00
Benedikt Tutzer
0371519c39 Added Monitor class that can monitor all changes in a Design or in a Module 2018-07-10 12:51:02 +02:00
Benedikt Tutzer
e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer
55df7fff19 removed debug output 2018-07-09 16:02:10 +02:00
Benedikt Tutzer
da8083dbd0 commands can now be run on arbitrary designs, not only on the active one 2018-07-09 16:01:56 +02:00
Benedikt Tutzer
8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
Benedikt Tutzer
7911379d4a Introduced namespace and removed class-prefixes to increase readability 2018-06-28 15:07:21 +02:00