N. Engelhardt
efe4d6dbdc
SigSpec/SigChunk::extract(): assert offset/length are not out of range
2024-01-25 12:28:17 +01:00
github-actions[bot]
80511ced71
Bump version
2024-01-25 00:16:42 +00:00
Krystine Sherwin
6e38848b92
Docs: updating makefiles
2024-01-25 12:35:03 +13:00
Krystine Sherwin
62d2f89c74
Revert artifact reuse
2024-01-25 12:18:06 +13:00
Krystine Sherwin
2a14c72110
test-docs: target examples directly
2024-01-25 11:36:59 +13:00
Krystine Sherwin
4ac983e56c
test-docs: Checkout Yosys
2024-01-25 11:32:39 +13:00
Krystine Sherwin
bb4d69005f
Docs: can we re-use build artifacts?
2024-01-25 10:15:43 +13:00
Krystine Sherwin
57a7532227
Docs: add test-examples target
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`test` becomes `test-macros`, with a new `test` calling both `test-*` targets.
2024-01-25 10:15:00 +13:00
Krystine Sherwin
e10d9b1fe0
Remove python dep from test-docs
2024-01-25 09:38:50 +13:00
Martin Povišer
6707db93b9
Merge pull request #4157 from whitequark/cxxrtl-fix-4144
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cxxrtl: fix typo in codegen for async set/clear
2024-01-24 18:48:45 +01:00
Martin Povišer
08fd47e970
Test roundtripping some processes to Verilog and back
2024-01-24 16:32:25 +00:00
Catherine
9cbfad2691
write_verilog: don't emit code with dangling else related to wrong condition.
2024-01-24 16:32:25 +00:00
Catherine
b841d1bcbe
cxxrtl: fix typo in codegen for async set/clear.
2024-01-24 16:30:01 +00:00
github-actions[bot]
3c3788ee28
Bump version
2024-01-24 00:16:36 +00:00
Krystine Sherwin
9b820108d6
Docs: add test-docs.yml
2024-01-24 11:22:38 +13:00
Krystine Sherwin
449135a9d4
Docs: adding other macro command lists
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Also updates `macro_commands.py` to skip empty lines, and moves comment
stripping earlier in parsing.
2024-01-24 10:29:40 +13:00
Krystine Sherwin
6c8949cacc
Docs: static opt macro list
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Also adds `docs/tests/macro_commands.py` which checks all commands in
`code_examples/macro_commands` against the current yosys build. Format similar
to `run-test.sh` files: logging the file under test and reporting errors.
2024-01-24 09:56:00 +13:00
Gabriel Gouvine
c634d59c18
Issue a warning instead of a syntax error for blif delay constraints
2024-01-23 16:25:16 +00:00
Miodrag Milanovic
ddfd867d29
hardcode iverilog version so it works on forkes and in PRs
2024-01-23 17:22:56 +01:00
Krystine Sherwin
95849edbba
Docs: changes from JF
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`yosys-witness` prereq `click`.
Yosys environment vars & `yosys --help` output.
Removing Ubuntu/macOS version numbers/names.
Hide `troubleshooting` page.
2024-01-23 17:35:06 +13:00
Krystine Sherwin
e63f1f5367
Docs: merge CI fix
2024-01-23 16:39:04 +13:00
github-actions[bot]
2f9fcc2e50
Bump version
2024-01-23 00:16:43 +00:00
Miodrag Milanović
3123dac77a
Merge pull request #4148 from YosysHQ/set_iverilog
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Checkout specific iverilog version (can be master as well)
2024-01-22 18:29:36 +01:00
Miodrag Milanovic
cfcd0b5729
Checkout specific iverilog version (can be master as well)
2024-01-22 17:18:39 +01:00
Catherine
3d9e44d182
hierarchy: keep display statements, like formal assertions.
2024-01-22 10:09:22 +00:00
Martin Povišer
2c4cf2b4b8
Merge pull request #4147 from stong/fix-typo
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Fix typo in stat help
2024-01-22 10:52:01 +01:00
Krystine Sherwin
9ec1536f1f
Docs: getting_started tidy
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Rename `show` intro and point to `/cmd/show`.
Add getting_started section overview.
2024-01-22 11:44:43 +13:00
Krystine Sherwin
65bb0d3059
Docs: updating to current 'master'
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Pulling for #4133 and removing related TODO.
2024-01-22 11:18:07 +13:00
Krystine Sherwin
794ad381c6
Docs: scripting_intro/show_intro
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Adds two new `show` commands to `fifo.ys` for demo purposes.
Mention referencing named selections with `@<name>`.
Also adds a note to `example_synth` to point to the show intro.
2024-01-22 11:10:02 +13:00
Stephen Tong
b3e7390c0e
Fix typo in stat help
2024-01-21 16:32:05 -05:00
github-actions[bot]
8649e30668
Bump version
2024-01-20 00:16:07 +00:00
Catherine
fc5ff7a265
cxxrtl: always lazily format print messages.
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This is mostly useful for collecting coverage for the future `$check`
cell, where, depending on the flavor, formatting a message may not be
wanted even for a failed assertion.
2024-01-19 18:55:23 +00:00
Miodrag Milanovic
b11449badb
Make small build links, and support verific small build
2024-01-19 16:30:35 +01:00
Catherine
b74d33d1b8
fmt: rename TIME to VLOG_TIME.
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The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.
This commit also simplifies the CXXRTL code generation for these format
specifiers.
2024-01-19 15:12:05 +00:00
Catherine
08d7f54726
cxxrtl: move a definition around. NFC
2024-01-19 15:12:05 +00:00
Jannis Harder
ac6fcb2547
write_aiger: Detect and error out on combinational loops
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Without this it will overflow the stack when loops are present.
2024-01-19 15:36:14 +01:00
Martin Povišer
cb86efa50c
celledges: Add test of shift cells edge data
2024-01-19 11:14:10 +01:00
Martin Povišer
134eb15c7e
celledges: Clean up shift rules
2024-01-19 11:08:31 +01:00
Miodrag Milanović
6282c1f27d
Merge pull request #4137 from yrabbit/bsram-infer
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gowin: fix the BRAM mapping.
2024-01-19 08:45:39 +01:00
YRabbit
ae991abf2e
gowin: fix the BRAM mapping.
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The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-19 15:26:37 +10:00
github-actions[bot]
7580821834
Bump version
2024-01-19 00:16:38 +00:00
N. Engelhardt
242ae4ef01
Merge pull request #4135 from YosysHQ/verific_clocking_fix
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Fix verific clocking when no driver exist
2024-01-18 15:40:35 +01:00
Miodrag Milanovic
1764c0ee3c
Fix verific clocking when no driver exist
2024-01-18 08:47:04 +01:00
Krystine Sherwin
14b7c581fa
Docs: reworking scripting_intro
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Now comes *after* example_synth, with references back to it.
Includes some minor adjustment to the `fifo.ys` script to better demonstrate the `select` command.
Still needs an updated section on `show`.
Also includes some other minor updates.
2024-01-18 15:33:59 +13:00
Krystine Sherwin
74d2c918cd
Docs: installation/source tree
2024-01-18 14:05:34 +13:00
Krystine Sherwin
93ceda5c63
Docs: auxlibs
2024-01-18 12:14:00 +13:00
N. Engelhardt
e1f4c5c9cb
Merge pull request #4133 from YosysHQ/show_color_proc
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show: allow setting colors via selection on PROC boxes
2024-01-17 17:56:53 +01:00
Martin Povišer
6a7fad4dd9
Merge pull request #4132 from povik/opt_lut_ice40
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opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-17 14:26:28 +01:00
Catherine
c4c55cb565
Merge pull request #4134 from whitequark/cxxrtl-capture-print
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CXXRTL: Allow capturing `$print` cell output
2024-01-17 13:13:15 +00:00
github-actions[bot]
37a6c9a097
Bump version
2024-01-17 00:16:14 +00:00
