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Docs: merge CI fix

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Krystine Sherwin 2024-01-23 16:39:04 +13:00
parent 9ec1536f1f 2f9fcc2e50
commit e63f1f5367
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5 changed files with 40 additions and 4 deletions
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5
.github/workflows/test-linux.yml vendored
View file

@ -85,13 +85,16 @@ jobs:
shell: bash
run: |
git clone https://github.com/steveicarus/iverilog.git
cd iverilog
git checkout ${{ vars.IVERILOG_VERSION }}
echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
- name: Cache iverilog
id: cache-iverilog
uses: actions/cache@v3
with:
path: .local/
key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
- name: Build iverilog
if: steps.cache-iverilog.outputs.cache-hit != 'true'

5
.github/workflows/test-macos.yml vendored
View file

@ -41,13 +41,16 @@ jobs:
shell: bash
run: |
git clone https://github.com/steveicarus/iverilog.git
cd iverilog
git checkout ${{ vars.IVERILOG_VERSION }}
echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
- name: Cache iverilog
id: cache-iverilog
uses: actions/cache@v3
with:
path: .local/
key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
- name: Build iverilog
if: steps.cache-iverilog.outputs.cache-hit != 'true'

2
Makefile
View file

@ -141,7 +141,7 @@ LDLIBS += -lrt
endif
endif
YOSYS_VER := 0.37+21
YOSYS_VER := 0.37+27
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo

2
passes/cmds/stat.cc
View file

@ -366,7 +366,7 @@ struct StatPass : public Pass {
log(" use cell area information from the provided liberty file\n");
log("\n");
log(" -tech <technology>\n");
log(" print area estemate for the specified technology. Currently supported\n");
log(" print area estimate for the specified technology. Currently supported\n");
log(" values for <technology>: xilinx, cmos\n");
log("\n");
log(" -width\n");

30
passes/hierarchy/hierarchy.cc
View file

@ -655,6 +655,17 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
log("Removed %d unused modules.\n", del_counter);
}
bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{
if (cache.count(mod) == 0)
for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type);
if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
return cache[mod] = true;
}
return cache[mod];
}
bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{
if (cache.count(mod) == 0)
@ -762,6 +773,11 @@ struct HierarchyPass : public Pass {
log(" -nodefaults\n");
log(" do not resolve input port default values\n");
log("\n");
log(" -nokeep_prints\n");
log(" per default this pass sets the \"keep\" attribute on all modules\n");
log(" that directly or indirectly display text on the terminal.\n");
log(" This option disables this behavior.\n");
log("\n");
log(" -nokeep_asserts\n");
log(" per default this pass sets the \"keep\" attribute on all modules\n");
log(" that directly or indirectly contain one or more formal properties.\n");
@ -818,6 +834,7 @@ struct HierarchyPass : public Pass {
bool keep_positionals = false;
bool keep_portwidths = false;
bool nodefaults = false;
bool nokeep_prints = false;
bool nokeep_asserts = false;
std::vector<std::string> generate_cells;
std::vector<generate_port_decl_t> generate_ports;
@ -893,6 +910,10 @@ struct HierarchyPass : public Pass {
nodefaults = true;
continue;
}
if (args[argidx] == "-nokeep_prints") {
nokeep_prints = true;
continue;
}
if (args[argidx] == "-nokeep_asserts") {
nokeep_asserts = true;
continue;
@ -1091,6 +1112,15 @@ struct HierarchyPass : public Pass {
}
}
if (!nokeep_prints) {
std::map<RTLIL::Module*, bool> cache;
for (auto mod : design->modules())
if (set_keep_print(cache, mod)) {
log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod));
mod->set_bool_attribute(ID::keep);
}
}
if (!nokeep_asserts) {
std::map<RTLIL::Module*, bool> cache;
for (auto mod : design->modules())