mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 13:29:12 +00:00
anlogic: support BRAM mapping
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng
parent
60c3ea367c
commit
c2b7ad3b28
8 changed files with 283 additions and 2 deletions
2
techlibs/anlogic/.gitignore
vendored
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2
techlibs/anlogic/.gitignore
vendored
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@ -0,0 +1,2 @@
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brams_init.mk
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brams_init_*.vh
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@ -3,6 +3,22 @@ OBJS += techlibs/anlogic/synth_anlogic.o
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OBJS += techlibs/anlogic/anlogic_eqn.o
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OBJS += techlibs/anlogic/anlogic_fixcarry.o
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GENFILES += techlibs/anlogic/brams_init_16.vh
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GENFILES += techlibs/anlogic/brams_init_9.vh
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GENFILES += techlibs/anlogic/brams_init_8.vh
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EXTRA_OBJS += techlibs/anlogic/brams_init.mk
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.SECONDARY: techlibs/anlogic/brams_init.mk
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techlibs/anlogic/brams_init.mk: techlibs/anlogic/brams_init.py
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$(Q) mkdir -p techlibs/anlogic
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$(P) $(PYTHON_EXECUTABLE) $<
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$(Q) touch $@
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techlibs/anlogic/brams_init_16.vh: techlibs/anlogic/brams_init.mk
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techlibs/anlogic/brams_init_9.vh: techlibs/anlogic/brams_init.mk
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techlibs/anlogic/brams_init_8.vh: techlibs/anlogic/brams_init.mk
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
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@ -10,3 +26,9 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))
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$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_16.vh))
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$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_9.vh))
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$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_8.vh))
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45
techlibs/anlogic/brams.txt
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45
techlibs/anlogic/brams.txt
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@ -0,0 +1,45 @@
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bram $__ANLOGIC_BRAM9K_TDP
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init 1
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abits 13 @a13d1
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dbits 1 @a13d1
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abits 12 @a12d2
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dbits 2 @a12d2
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abits 11 @a11d4
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dbits 4 @a11d4
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abits 10 @a10d8
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dbits 8 @a10d8
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abits 10 @a10d9
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dbits 9 @a10d9
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__ANLOGIC_BRAM32K
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init 1
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abits 11
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dbits 16
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 2
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__ANLOGIC_BRAM32K
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min efficiency 30
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__ANLOGIC_BRAM9K_TDP
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min efficiency 5
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make_transp
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endmatch
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21
techlibs/anlogic/brams_init.py
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21
techlibs/anlogic/brams_init.py
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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with open("techlibs/anlogic/brams_init_9.vh", "w") as f:
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for i in range(4):
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init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
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for k in range(4, 256, 4):
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init_snippets[k] = "\n " + init_snippets[k]
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print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
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for i in range(32):
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init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
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for k in range(4, 32, 4):
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init_snippets[k] = "\n " + init_snippets[k]
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print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
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with open("techlibs/anlogic/brams_init_8.vh", "w") as f:
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for i in range(32):
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print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
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with open("techlibs/anlogic/brams_init_16.vh", "w") as f:
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for i in range(128):
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print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
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162
techlibs/anlogic/brams_map.v
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162
techlibs/anlogic/brams_map.v
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@ -0,0 +1,162 @@
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module \$__ANLOGIC_BRAM9K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 9;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [9215:0] INIT = 9216'bx;
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parameter TRANSP2 = 0;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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localparam CLKAMUX = CLKPOL2 ? "SIG" : "INV";
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localparam CLKBMUX = CLKPOL3 ? "SIG" : "INV";
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localparam WRITEMODE_B = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
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localparam DATA_WIDTH = CFG_DBITS == 1 ? "1" :
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(CFG_DBITS == 2 ? "2" :
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(CFG_DBITS <= 4 ? "4" : "9"));
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localparam APADBITS = $clog2(CFG_DBITS == 9 ? 8 : CFG_DBITS);
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wire [12:0] addra;
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wire [12:0] addrb;
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assign addra[12:APADBITS] = A1ADDR;
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assign addrb[12:APADBITS] = B1ADDR;
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wire [8:0] doa;
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wire [8:0] dib;
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assign A1DATA[CFG_DBITS-1:0] = doa;
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assign dib[CFG_DBITS-1:0] = B1DATA;
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generate if (CFG_DBITS == 9) begin
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EG_PHY_BRAM #(
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.MODE("DP8K"),
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.DATA_WIDTH_A(DATA_WIDTH),
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.DATA_WIDTH_B(DATA_WIDTH),
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.READBACK("OFF"),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.WRITEMODE_A("READBEFOREWRITE"),
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.WRITEMODE_B(WRITEMODE_B),
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.RESETMODE("ASYNC"),
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.CEAMUX("SIG"), .CEBMUX("SIG"),
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.OCEAMUX("1"), .OCEBMUX("1"),
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.RSTAMUX("0"), .RSTBMUX("0"),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WEAMUX("0"), .WEBMUX("SIG"),
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.CSA0("1"), .CSA1("1"),
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.CSA2("1"), .CSB0("1"),
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.CSB1("1"), .CSB2("1"),
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`include "brams_init_9.vh"
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) _TECHMAP_REPLACE_ (
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.doa(doa), .dib(dib),
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.addra(addra), .addrb(addrb),
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.clka(CLK2), .clkb(CLK3),
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.cea(A1EN), .ceb(B1EN),
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.ocea(1'b1), .oceb(1'b1),
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.rsta(1'b0), .rstb(1'b0),
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.wea(1'b0), .web(B1EN),
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.csa(3'b111), .csb(3'b111)
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);
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end else begin
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EG_PHY_BRAM #(
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.MODE("DP8K"),
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.DATA_WIDTH_A(DATA_WIDTH),
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.DATA_WIDTH_B(DATA_WIDTH),
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.READBACK("OFF"),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.WRITEMODE_A("READBEFOREWRITE"),
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.WRITEMODE_B(WRITEMODE_B),
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.RESETMODE("ASYNC"),
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.CEAMUX("SIG"), .CEBMUX("SIG"),
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.OCEAMUX("1"), .OCEBMUX("1"),
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.RSTAMUX("0"), .RSTBMUX("0"),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WEAMUX("0"), .WEBMUX("SIG"),
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.CSA0("1"), .CSA1("1"),
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.CSA2("1"), .CSB0("1"),
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.CSB1("1"), .CSB2("1"),
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`include "brams_init_8.vh"
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) _TECHMAP_REPLACE_ (
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.doa(doa), .dib(dib),
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.addra(addra), .addrb(addrb),
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.clka(CLK2), .clkb(CLK3),
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.cea(A1EN), .ceb(B1EN),
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.ocea(1'b1), .oceb(1'b1),
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.rsta(1'b0), .rstb(1'b0),
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.wea(1'b0), .web(B1EN),
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.csa(3'b111), .csb(3'b111)
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);
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end endgenerate
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endmodule
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module \$__ANLOGIC_BRAM32K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 11;
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parameter CFG_DBITS = 16;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [32767:0] INIT = 32768'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [1:0] B1EN;
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localparam CLKAMUX = CLKPOL2 ? "SIG" : "INV";
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localparam CLKBMUX = CLKPOL3 ? "SIG" : "INV";
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wire byteweb = B1EN[1] ^ B1EN[0];
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wire byteb = B1EN[1];
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EG_PHY_BRAM32K #(
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.MODE("DP16K"),
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.DATA_WIDTH_A("16"),
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.DATA_WIDTH_B("16"),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.WRITEMODE_A("NORMAL"),
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.WRITEMODE_B("NORMAL"),
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.SRMODE("ASYNC"),
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.CSAMUX("SIG"), .CSBMUX("SIG"),
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.OCEAMUX("1"), .OCEBMUX("1"),
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.RSTAMUX("0"), .RSTBMUX("0"),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WEAMUX("0"), .WEBMUX("SIG"),
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.READBACK("OFF"),
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`include "brams_init_16.vh"
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) _TECHMAP_REPLACE_ (
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.doa(A1DATA), .dib(B1DATA),
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.addra(A1ADDR), .addrb(B1ADDR),
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.bytea(1'b0), .byteb(byteb),
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.bytewea(1'b0), .byteweb(byteweb),
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.csa(A1EN), .csb(|B1EN),
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.wea(1'b0), .web(|B1EN),
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.clka(CLK2), .clkb(CLK3),
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.rsta(1'b0), .rstb(1'b0),
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.ocea(1'b1), .oceb(1'b1)
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);
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endmodule
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@ -63,6 +63,9 @@ struct SynthAnlogicPass : public ScriptPass
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log(" -nolutram\n");
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log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use EG_PHY_BRAM or EG_PHY_BRAM32K cells in output netlist\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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@ -70,7 +73,7 @@ struct SynthAnlogicPass : public ScriptPass
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}
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string top_opt, edif_file, json_file;
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bool flatten, retime, nolutram;
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bool flatten, retime, nolutram, nobram;
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void clear_flags() override
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{
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@ -80,6 +83,7 @@ struct SynthAnlogicPass : public ScriptPass
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flatten = true;
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retime = false;
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nolutram = false;
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nobram = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -118,6 +122,10 @@ struct SynthAnlogicPass : public ScriptPass
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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@ -158,6 +166,14 @@ struct SynthAnlogicPass : public ScriptPass
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run("synth -run coarse");
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}
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if (!nobram && check_label("map_bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/anlogic/brams.txt");
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run("techmap -map +/anlogic/brams_map.v");
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run("setundef -zero -params t:EG_PHY_BRAM");
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run("setundef -zero -params t:EG_PHY_BRAM32K");
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}
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if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
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{
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run("memory_bram -rules +/anlogic/lutrams.txt");
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13
tests/arch/anlogic/blockram.ys
Normal file
13
tests/arch/anlogic/blockram.ys
Normal file
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@ -0,0 +1,13 @@
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sp
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proc
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memory -nomap
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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memory
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opt -full
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design -load postopt
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cd sync_ram_sp
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select -assert-count 1 t:EG_PHY_BRAM
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select -assert-none t:EG_PHY_BRAM %% t:* %D
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@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram
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memory
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opt -full
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