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https://github.com/YosysHQ/yosys
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c2b7ad3b28
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
35 lines
1.6 KiB
Makefile
35 lines
1.6 KiB
Makefile
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OBJS += techlibs/anlogic/synth_anlogic.o
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OBJS += techlibs/anlogic/anlogic_eqn.o
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OBJS += techlibs/anlogic/anlogic_fixcarry.o
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GENFILES += techlibs/anlogic/brams_init_16.vh
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GENFILES += techlibs/anlogic/brams_init_9.vh
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GENFILES += techlibs/anlogic/brams_init_8.vh
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EXTRA_OBJS += techlibs/anlogic/brams_init.mk
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.SECONDARY: techlibs/anlogic/brams_init.mk
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techlibs/anlogic/brams_init.mk: techlibs/anlogic/brams_init.py
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$(Q) mkdir -p techlibs/anlogic
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$(P) $(PYTHON_EXECUTABLE) $<
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$(Q) touch $@
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techlibs/anlogic/brams_init_16.vh: techlibs/anlogic/brams_init.mk
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techlibs/anlogic/brams_init_9.vh: techlibs/anlogic/brams_init.mk
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techlibs/anlogic/brams_init_8.vh: techlibs/anlogic/brams_init.mk
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))
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$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_16.vh))
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$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_9.vh))
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$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_8.vh))
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