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Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
46 lines
657 B
Plaintext
46 lines
657 B
Plaintext
bram $__ANLOGIC_BRAM9K_TDP
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init 1
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abits 13 @a13d1
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dbits 1 @a13d1
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abits 12 @a12d2
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dbits 2 @a12d2
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abits 11 @a11d4
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dbits 4 @a11d4
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abits 10 @a10d8
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dbits 8 @a10d8
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abits 10 @a10d9
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dbits 9 @a10d9
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__ANLOGIC_BRAM32K
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init 1
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abits 11
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dbits 16
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 2
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__ANLOGIC_BRAM32K
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min efficiency 30
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__ANLOGIC_BRAM9K_TDP
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min efficiency 5
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make_transp
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endmatch
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