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Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
22 lines
948 B
Python
22 lines
948 B
Python
#!/usr/bin/env python3
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with open("techlibs/anlogic/brams_init_9.vh", "w") as f:
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for i in range(4):
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init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
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for k in range(4, 256, 4):
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init_snippets[k] = "\n " + init_snippets[k]
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print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
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for i in range(32):
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init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
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for k in range(4, 32, 4):
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init_snippets[k] = "\n " + init_snippets[k]
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print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
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with open("techlibs/anlogic/brams_init_8.vh", "w") as f:
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for i in range(32):
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print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
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with open("techlibs/anlogic/brams_init_16.vh", "w") as f:
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for i in range(128):
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print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
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