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Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs

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aiger: fix -map and -vmap
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Emil J 2025-06-02 15:07:19 +02:00 • committed by GitHub
commit c21cd300a0
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2 changed files with 11 additions and 1 deletions
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2
backends/aiger/aiger.cc
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@ -713,7 +713,7 @@ struct AigerWriter
}
if (wire->port_output) {
int o = ordered_outputs.at(sig[i]);
int o = ordered_outputs.at(SigSpec(wire, i));
output_lines[o] += stringf("output %d %d %s\n", o, index, log_id(wire));
}

10
tests/aiger/io.ys Normal file
View file

@ -0,0 +1,10 @@
read_verilog <<EOF
module bad(
input in,
output reg [1:0] out
);
assign out = {in, 1'b0};
endmodule
EOF
proc
write_aiger -vmap /dev/null /dev/null