From 2522bcd49272d9a2b9ef68cbe8bf2bd27a581cbb Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 9 May 2025 14:21:10 +0200
Subject: [PATCH 1/2] aiger: fix -map and -vmap

---
 backends/aiger/aiger.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index f2cb5d9bc..0e5706a75 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -698,7 +698,7 @@ struct AigerWriter
 				}
 
 				if (wire->port_output) {
-					int o = ordered_outputs.at(sig[i]);
+					int o = ordered_outputs.at(SigSpec(wire, i));
 					output_lines[o] += stringf("output %d %d %s\n", o, index, log_id(wire));
 				}
 

From cbf069849ec48669b67b8252e04662acc3a75eb6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Emil=20Ji=C5=99=C3=AD=20Tywoniak?= <emil.tywoniak@gmail.com>
Date: Fri, 9 May 2025 16:01:47 +0200
Subject: [PATCH 2/2] aiger: add regression test for sliced output segfault

---
 tests/aiger/io.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/aiger/io.ys

diff --git a/tests/aiger/io.ys b/tests/aiger/io.ys
new file mode 100644
index 000000000..eae7f358d
--- /dev/null
+++ b/tests/aiger/io.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOF
+module bad(
+	input in,
+	output reg [1:0] out
+);
+	assign out = {in, 1'b0};
+endmodule
+EOF
+proc
+write_aiger -vmap /dev/null /dev/null