mirror of
https://github.com/YosysHQ/yosys
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docs: restructuring images directory
see also previous commit Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
This commit is contained in:
Krystine Sherwin
parent
dbc38d72cf
commit
b6e61c16b1
44 changed files with 131 additions and 237 deletions
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@ -1,13 +1,10 @@
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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all: counter_00.dot counter_01.dot counter_02.dot counter_03.dot
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DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot
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counter_00.dot: counter.v counter.ys mycells.lib
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dots: $(DOTS)
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$(DOTS): counter.v counter.ys mycells.lib
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$(YOSYS) counter_outputs.ys
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counter_01.dot: counter_00.dot
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counter_02.dot: counter_00.dot
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counter_03.dot: counter_00.dot
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@ -1,12 +1,14 @@
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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all: macc_simple_xmap.pdf macc_xilinx_xmap.pdf
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DOTS = macc_simple_xmap.dot macc_xilinx_xmap.dot
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macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
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dots: $(DOTS)
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macc_simple_xmap.dot: macc_simple_*.v macc_simple_test.ys
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$(YOSYS) macc_simple_test.ys
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macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
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macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
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$(YOSYS) macc_xilinx_test.ys
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@ -3,21 +3,21 @@ read_verilog -lib -icells macc_xilinx_unwrap_map.v
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read_verilog -lib -icells macc_xilinx_xmap.v
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hierarchy -check ;;
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show -prefix macc_xilinx_test1a -format pdf -notitle test1
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show -prefix macc_xilinx_test2a -format pdf -notitle test2
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show -prefix macc_xilinx_test1a -format dot -notitle test1
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show -prefix macc_xilinx_test2a -format dot -notitle test2
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techmap -map macc_xilinx_swap_map.v;;
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show -prefix macc_xilinx_test1b -format pdf -notitle test1
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show -prefix macc_xilinx_test2b -format pdf -notitle test2
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show -prefix macc_xilinx_test1b -format dot -notitle test1
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show -prefix macc_xilinx_test2b -format dot -notitle test2
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
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-unsigned $__add_wrapper Y Y_WIDTH;;
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show -prefix macc_xilinx_test1c -format pdf -notitle test1
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show -prefix macc_xilinx_test2c -format pdf -notitle test2
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show -prefix macc_xilinx_test1c -format dot -notitle test1
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show -prefix macc_xilinx_test2c -format dot -notitle test2
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design -push
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read_verilog macc_xilinx_xmap.v
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@ -30,14 +30,14 @@ extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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show -prefix macc_xilinx_test1d -format pdf -notitle test1
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show -prefix macc_xilinx_test2d -format pdf -notitle test2
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show -prefix macc_xilinx_test1d -format dot -notitle test1
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show -prefix macc_xilinx_test2d -format dot -notitle test2
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techmap -map macc_xilinx_unwrap_map.v;;
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show -prefix macc_xilinx_test1e -format pdf -notitle test1
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show -prefix macc_xilinx_test2e -format pdf -notitle test2
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show -prefix macc_xilinx_test1e -format dot -notitle test1
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show -prefix macc_xilinx_test2e -format dot -notitle test2
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design -load __macc_xilinx_xmap
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show -prefix macc_xilinx_xmap -format pdf -notitle
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show -prefix macc_xilinx_xmap -format dot -notitle
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@ -1,8 +1,8 @@
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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all: scrambler_p01.dot scrambler_p02.dot
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dots: scrambler_p01.dot scrambler_p02.dot
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scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v
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$(YOSYS) scrambler.ys
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@ -11,22 +11,22 @@ MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO))
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SUBMOD = submod_00 submod_01 submod_02 submod_03
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SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD))
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all: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS)
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dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS)
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select.dot: select.v select.ys
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$(YOSYS) select.ys
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$(SUMPROD_DOTS): sumprod.v
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$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
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$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
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$(YOSYS) -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
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$(YOSYS) -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
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$(YOSYS) -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
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$(YOSYS) -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod; show -format dot -prefix sumprod_02'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05'
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$(MEMDEMO_DOTS): memdemo.v
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$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
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$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
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$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00'
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$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff'
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$(SUBMOD_DOTS): submod.ys memdemo.v
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$(YOSYS) submod.ys
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@ -2,16 +2,16 @@ PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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EXAMPLE = example_00 example_01 example_02 example_03
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EXAMPLE = example_00 example_01 example_02
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EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
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CMOS = cmos_00 cmos_01
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CMOS_DOTS := $(addsuffix .dot,$(CMOS))
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all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
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dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
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splice.dot: splice.v
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$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
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$(YOSYS) -p 'read_verilog splice.v; proc; opt; show -format dot -prefix splice'
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$(EXAMPLE_DOTS): example.v example.ys
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$(YOSYS) example.ys
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@ -4,8 +4,3 @@ proc
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show -format dot -prefix example_01
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opt
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show -format dot -prefix example_02
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cd example
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select t:$add
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show -format dot -prefix example_03
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@ -1,3 +1,5 @@
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dots:
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test: stubnets.so
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yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
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yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
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@ -7,18 +7,15 @@ TARGETS += abc_01
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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all: $(addsuffix .pdf,$(TARGETS))
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DOTS = $(addsuffix .dot,$(TARGETS))
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define make_pdf_template
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$(1).pdf: $(1)*.v $(1)*.ys
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$(YOSYS) -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
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endef
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dots: $(DOTS)
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$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
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%.dot: %.v %.ys
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$(YOSYS) -p 'script $*.ys; show -notitle -prefix $* -format dot'
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clean:
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rm -f $(addsuffix .pdf,$(TARGETS))
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rm -f $(addsuffix .dot,$(TARGETS))
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rm -f $(DOTS)
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@ -1,8 +1,8 @@
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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all: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
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dots: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
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red_or3x1.dot: red_or3x1_*
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$(YOSYS) red_or3x1_test.ys
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@ -18,4 +18,3 @@ mulshift.dot: mulshift_*
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addshift.dot: addshift_*
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$(YOSYS) addshift_test.ys
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