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https://github.com/YosysHQ/yosys
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b6e61c16b1
see also previous commit Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
33 lines
1.5 KiB
Makefile
33 lines
1.5 KiB
Makefile
PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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SUMPROD = sumprod_00 sumprod_01 sumprod_02 sumprod_03 sumprod_04 sumprod_05
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SUMPROD_DOTS := $(addsuffix .dot,$(SUMPROD))
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MEMDEMO = memdemo_00 memdemo_01
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MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO))
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SUBMOD = submod_00 submod_01 submod_02 submod_03
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SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD))
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dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS)
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select.dot: select.v select.ys
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$(YOSYS) select.ys
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$(SUMPROD_DOTS): sumprod.v
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod; show -format dot -prefix sumprod_02'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04'
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$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05'
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$(MEMDEMO_DOTS): memdemo.v
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$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00'
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$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff'
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$(SUBMOD_DOTS): submod.ys memdemo.v
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$(YOSYS) submod.ys
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