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https://github.com/YosysHQ/yosys
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b6e61c16b1
see also previous commit Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
24 lines
737 B
Makefile
24 lines
737 B
Makefile
PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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EXAMPLE = example_00 example_01 example_02
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EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
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CMOS = cmos_00 cmos_01
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CMOS_DOTS := $(addsuffix .dot,$(CMOS))
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dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
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splice.dot: splice.v
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$(YOSYS) -p 'read_verilog splice.v; proc; opt; show -format dot -prefix splice'
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$(EXAMPLE_DOTS): example.v example.ys
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$(YOSYS) example.ys
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cmos_00.dot: cmos.v
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$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
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cmos_01.dot: cmos.v
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$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'
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