mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-26 20:08:44 +00:00
Code Activity

Merge 2ed89e02da into 967b47d984

Browse source
This commit is contained in:
Dhaval 2026-01-15 08:10:44 +01:00 • committed by GitHub
commit a625a95d5f
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 26 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

17
backends/verilog/verilog_backend.cc
View file

@ -386,14 +386,31 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
f << "{0{1'b0}}";
return;
}
if (sig.is_fully_const() && GetSize(sig) > 8192) {
f << stringf("{ ");
int i = 0;
auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
dump_const(f, it->data, 1, 0);
if (it != chunks.rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
}
f << stringf(" }");
return;
}
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
} else {
f << stringf("{ ");
int i = 0;
auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
if (it != chunks.rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
dump_sigchunk(f, *it, true);
}
f << stringf(" }");

11
frontends/verific/verific.cc
View file

@ -109,6 +109,7 @@ int verific_verbose;
bool verific_import_pending;
string verific_error_msg;
int verific_sva_fsm_limit;
bool verific_no_split_complex_ports = false; // disable splitting of complex ports
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@ -3061,8 +3062,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg);
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
if (!verific_no_split_complex_ports)
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
VerificExtNets worker;
for (auto nl : nl_todo)
@ -3692,6 +3694,11 @@ struct VerificPass : public Pass {
break;
}
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
goto check_error;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{