diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 3d451117c..251cf1443 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -386,14 +386,31 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 		f << "{0{1'b0}}";
 		return;
 	}
+	if (sig.is_fully_const() && GetSize(sig) > 8192) {
+		f << stringf("{ ");
+		int i = 0;
+		auto chunks = sig.chunks();
+		for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
+			dump_const(f, it->data, 1, 0);
+			if (it != chunks.rbegin())
+				f << stringf(", ");
+			if (i++ % 20 == 19)
+				f << stringf("\n");
+		}
+		f << stringf(" }");
+		return;
+	}
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
 	} else {
 		f << stringf("{ ");
+		int i = 0;
 		auto chunks = sig.chunks();
 		for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
 			if (it != chunks.rbegin())
 				f << stringf(", ");
+			if (i++ % 20 == 19)
+				f << stringf("\n");
 			dump_sigchunk(f, *it, true);
 		}
 		f << stringf(" }");
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5790e92f0..b2b83f105 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -109,6 +109,7 @@ int verific_verbose;
 bool verific_import_pending;
 string verific_error_msg;
 int verific_sva_fsm_limit;
+bool verific_no_split_complex_ports = false; // disable splitting of complex ports
 
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@@ -3061,8 +3062,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 	if (!verific_error_msg.empty())
 		log_error("%s\n", verific_error_msg);
 
-	for (auto nl : nl_todo)
-		nl.second->ChangePortBusStructures(1 /* hierarchical */);
+	if (!verific_no_split_complex_ports)
+		for (auto nl : nl_todo)
+			nl.second->ChangePortBusStructures(1 /* hierarchical */);
 
 	VerificExtNets worker;
 	for (auto nl : nl_todo)
@@ -3692,6 +3694,11 @@ struct VerificPass : public Pass {
 			break;
 		}
 
+		if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
+			verific_no_split_complex_ports = true;
+			goto check_error;
+		}
+
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
 		{