From af810b3449c9dd6727820164976dcf884074cbd1 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Sun, 4 Jan 2026 12:06:23 +0530 Subject: [PATCH 1/3] verific: add option to disable splitting of complex ports --- frontends/verific/verific.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5790e92f0..283dafa27 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -109,6 +109,7 @@ int verific_verbose; bool verific_import_pending; string verific_error_msg; int verific_sva_fsm_limit; +bool verific_no_split_complex_ports = false; // disable splitting of complex ports #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT vector verific_incdirs, verific_libdirs, verific_libexts; @@ -3061,8 +3062,9 @@ std::string verific_import(Design *design, const std::mapChangePortBusStructures(1 /* hierarchical */); + if (!verific_no_split_complex_ports) + for (auto nl : nl_todo) + nl.second->ChangePortBusStructures(1 /* hierarchical */); VerificExtNets worker; for (auto nl : nl_todo) @@ -3693,6 +3695,10 @@ struct VerificPass : public Pass { } #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") { + verific_no_split_complex_ports = true; + goto check_error; + } if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; From bc7f0bb4c78be9f38a92c8e948a2cf5203f8627c Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Sun, 4 Jan 2026 12:08:43 +0530 Subject: [PATCH 2/3] fix --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 283dafa27..9580e6fc0 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3697,7 +3697,7 @@ struct VerificPass : public Pass { #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") { verific_no_split_complex_ports = true; - goto check_error; + continue; } if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { From 2ed89e02daca1d841235e2aa2b267dc8b6f0b549 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Mon, 5 Jan 2026 23:26:02 +0530 Subject: [PATCH 3/3] move outside of VERIFIC_SYSTEMVERILOG_SUPPORT --- backends/verilog/verilog_backend.cc | 17 +++++++++++++++++ frontends/verific/verific.cc | 5 +++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 8d77160fd..38a3a11da 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -386,14 +386,31 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) f << "{0{1'b0}}"; return; } + if (sig.is_fully_const() && GetSize(sig) > 8192) { + f << stringf("{ "); + int i = 0; + auto chunks = sig.chunks(); + for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) { + dump_const(f, it->data, 1, 0); + if (it != chunks.rbegin()) + f << stringf(", "); + if (i++ % 20 == 19) + f << stringf("\n"); + } + f << stringf(" }"); + return; + } if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); } else { f << stringf("{ "); + int i = 0; auto chunks = sig.chunks(); for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) { if (it != chunks.rbegin()) f << stringf(", "); + if (i++ % 20 == 19) + f << stringf("\n"); dump_sigchunk(f, *it, true); } f << stringf(" }"); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9580e6fc0..b2b83f105 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3694,11 +3694,12 @@ struct VerificPass : public Pass { break; } -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") { verific_no_split_complex_ports = true; - continue; + goto check_error; } + +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED;