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move outside of VERIFIC_SYSTEMVERILOG_SUPPORT

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This commit is contained in:
Dhaval Chaudhari 2026-01-05 23:26:02 +05:30
parent bc7f0bb4c7
commit 2ed89e02da
2 changed files with 20 additions and 2 deletions
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17
backends/verilog/verilog_backend.cc
View file

@ -386,14 +386,31 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
f << "{0{1'b0}}";
return;
}
if (sig.is_fully_const() && GetSize(sig) > 8192) {
f << stringf("{ ");
int i = 0;
auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
dump_const(f, it->data, 1, 0);
if (it != chunks.rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
}
f << stringf(" }");
return;
}
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
} else {
f << stringf("{ ");
int i = 0;
auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
if (it != chunks.rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
dump_sigchunk(f, *it, true);
}
f << stringf(" }");

5
frontends/verific/verific.cc
View file

@ -3694,11 +3694,12 @@ struct VerificPass : public Pass {
break;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
continue;
goto check_error;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{
unsigned verilog_mode = veri_file::UNDEFINED;