From 94c789e9c86824d40c4c5bdd9d7ea9d33ccfdb78 Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Wed, 4 Mar 2026 17:48:35 -0500 Subject: [PATCH 1/9] setundef: respect selection for cells, processes, and connections Previously, setundef would rewrite sigspecs in all cells, processes, and connections regardless of the active selection. Only modules and memories were correctly filtered by selection. Fix by using module->selected_cells() for cells, adding a module->selected() check for processes, and checking wire selection on the lhs of each connection before rewriting. Fixes #5624 --- passes/cmds/setundef.cc | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 5d2ccfcc8..b3d76a51f 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -502,14 +502,22 @@ struct SetundefPass : public Pass { } } - for (auto &it : module->cells_) - if (!it.second->get_bool_attribute(ID::xprop_decoder)) - it.second->rewrite_sigspecs(worker); + for (auto cell : module->selected_cells()) + if (!cell->get_bool_attribute(ID::xprop_decoder)) + cell->rewrite_sigspecs(worker); for (auto &it : module->processes) - it.second->rewrite_sigspecs(worker); + if (module->selected(it.second)) + it.second->rewrite_sigspecs(worker); for (auto &it : module->connections_) { - worker(it.first); - worker(it.second); + SigSpec lhs = it.first; + bool selected = false; + for (auto &chunk : lhs.chunks()) + if (chunk.wire && module->design->selected(module, chunk.wire)) + selected = true; + if (selected) { + worker(it.first); + worker(it.second); + } } if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST) From 4e54853e3550669cdabd2fbd8b7a2f754c31dcbb Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Thu, 5 Mar 2026 11:16:07 -0500 Subject: [PATCH 2/9] setundef: use selected_processes() per review feedback --- passes/cmds/setundef.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index b3d76a51f..e592d5be0 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -505,9 +505,8 @@ struct SetundefPass : public Pass { for (auto cell : module->selected_cells()) if (!cell->get_bool_attribute(ID::xprop_decoder)) cell->rewrite_sigspecs(worker); - for (auto &it : module->processes) - if (module->selected(it.second)) - it.second->rewrite_sigspecs(worker); + for (auto &it : module->selected_processes()) + it.second->rewrite_sigspecs(worker); for (auto &it : module->connections_) { SigSpec lhs = it.first; bool selected = false; From df283fa1c9a67fff7cfa6898eb95ab0880b3a67e Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Thu, 5 Mar 2026 11:22:00 -0500 Subject: [PATCH 3/9] setundef: use selected_processes() per review feedback --- passes/cmds/setundef.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e592d5be0..792b9b12c 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -506,7 +506,7 @@ struct SetundefPass : public Pass { if (!cell->get_bool_attribute(ID::xprop_decoder)) cell->rewrite_sigspecs(worker); for (auto &it : module->selected_processes()) - it.second->rewrite_sigspecs(worker); + it->rewrite_sigspecs(worker); for (auto &it : module->connections_) { SigSpec lhs = it.first; bool selected = false; From 6cd66aed47e69bac3e820b9d9e2150a5fa900466 Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Thu, 5 Mar 2026 17:51:01 -0500 Subject: [PATCH 4/9] setundef: rename process loop variable and respect selection in -init mode --- passes/cmds/setundef.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 792b9b12c..ecbada2f8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -417,6 +417,9 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; + if (!design->selected(module, wire)) + continue; + if (!wire->attributes.count(ID::init)) continue; @@ -446,6 +449,9 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; + if (!design->selected(module, wire)) + continue; + for (auto bit : sigmap(wire)) if (!ffbits.count(bit)) goto next_wire; @@ -467,6 +473,9 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; + if (!design->selected(module, wire)) + continue; + for (auto bit : sigmap(wire)) if (ffbits.count(bit)) initwires.insert(wire); @@ -505,8 +514,8 @@ struct SetundefPass : public Pass { for (auto cell : module->selected_cells()) if (!cell->get_bool_attribute(ID::xprop_decoder)) cell->rewrite_sigspecs(worker); - for (auto &it : module->selected_processes()) - it->rewrite_sigspecs(worker); + for (auto proc : module->selected_processes()) + proc->rewrite_sigspecs(worker); for (auto &it : module->connections_) { SigSpec lhs = it.first; bool selected = false; From 9e666c727f83f37ae88a86139fe4fd737392ec88 Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Fri, 6 Mar 2026 10:37:59 -0500 Subject: [PATCH 5/9] setundef: respect selection in -undriven mode --- passes/cmds/setundef.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index ecbada2f8..5d9a7d1cb 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -310,6 +310,8 @@ struct SetundefPass : public Pass { RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { + if (!design->selected(module, c.wire)) + continue; RTLIL::Wire * wire; if (c.wire->width == c.width) { wire = c.wire; @@ -343,6 +345,8 @@ struct SetundefPass : public Pass { RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { + if (!design->selected(module, c.wire)) + continue; RTLIL::SigSpec bits; if (worker.next_bit_mode == MODE_ANYSEQ) bits = module->Anyseq(NEW_ID, c.width); From 5048dac8542a30d3a2855d203820c4c153b3660b Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Fri, 6 Mar 2026 18:12:03 -0500 Subject: [PATCH 6/9] setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer --- passes/cmds/setundef.cc | 23 ++++++---------------- tests/various/setundef_selection.ys | 27 ++++++++++++++++++++++++++ tests/various/setundef_selection_ff.il | 19 ++++++++++++++++++ 3 files changed, 52 insertions(+), 17 deletions(-) create mode 100644 tests/various/setundef_selection.ys create mode 100644 tests/various/setundef_selection_ff.il diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 5d9a7d1cb..cdd7f3446 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -330,12 +330,12 @@ struct SetundefPass : public Pass { SigMap sigmap(module); SigPool undriven_signals; - for (auto &it : module->wires_) - undriven_signals.add(sigmap(it.second)); + for (auto wire : module->selected_wires()) + undriven_signals.add(sigmap(wire)); - for (auto &it : module->wires_) - if (it.second->port_input) - undriven_signals.del(sigmap(it.second)); + for (auto wire : module->selected_wires()) + if (wire->port_input) + undriven_signals.del(sigmap(wire)); CellTypes ct(design); for (auto &it : module->cells_) @@ -345,8 +345,6 @@ struct SetundefPass : public Pass { RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { - if (!design->selected(module, c.wire)) - continue; RTLIL::SigSpec bits; if (worker.next_bit_mode == MODE_ANYSEQ) bits = module->Anyseq(NEW_ID, c.width); @@ -366,7 +364,7 @@ struct SetundefPass : public Pass { pool ffbits; pool initwires; - for (auto cell : module->cells()) + for (auto cell : module->selected_cells()) { if (!cell->is_builtin_ff()) continue; @@ -421,9 +419,6 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; - if (!design->selected(module, wire)) - continue; - if (!wire->attributes.count(ID::init)) continue; @@ -453,9 +448,6 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; - if (!design->selected(module, wire)) - continue; - for (auto bit : sigmap(wire)) if (!ffbits.count(bit)) goto next_wire; @@ -477,9 +469,6 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; - if (!design->selected(module, wire)) - continue; - for (auto bit : sigmap(wire)) if (ffbits.count(bit)) initwires.insert(wire); diff --git a/tests/various/setundef_selection.ys b/tests/various/setundef_selection.ys new file mode 100644 index 000000000..8d11bcf9e --- /dev/null +++ b/tests/various/setundef_selection.ys @@ -0,0 +1,27 @@ +# Test that setundef -zero respects wire selection: only selected wire is changed +read_verilog < Date: Sun, 8 Mar 2026 18:15:35 -0400 Subject: [PATCH 7/9] I think CI runs within the tests directory based on error so I changed the file path --- tests/various/setundef_selection.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/setundef_selection.ys b/tests/various/setundef_selection.ys index 8d11bcf9e..67df8bed9 100644 --- a/tests/various/setundef_selection.ys +++ b/tests/various/setundef_selection.ys @@ -20,7 +20,7 @@ sat -prove b 0 design -reset # Test that setundef -init respects cell selection: only selected FF gets init set -read_rtlil tests/various/setundef_selection_ff.il +read_rtlil setundef_selection_ff.il setundef -init -zero c:myff_a # only wire a should have init attribute, not b select -assert-count 1 w:* a:init %i From 47c2257f82f25f75175e0a41e9ca1b37d653bf6a Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Sun, 8 Mar 2026 19:41:31 -0400 Subject: [PATCH 8/9] setundef: more tests! and wire selection in -init mode --- passes/cmds/setundef.cc | 10 +++++++++- tests/various/setundef_selection.ys | 17 +++++++++++------ tests/various/setundef_selection_undriven.il | 4 ++++ 3 files changed, 24 insertions(+), 7 deletions(-) create mode 100644 tests/various/setundef_selection_undriven.il diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index cdd7f3446..99a223bdc 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -364,11 +364,19 @@ struct SetundefPass : public Pass { pool ffbits; pool initwires; - for (auto cell : module->selected_cells()) + for (auto cell : module->cells()) { if (!cell->is_builtin_ff()) continue; + bool cell_selected = design->selected(module, cell); + bool wire_selected = false; + for (auto bit : sigmap(cell->getPort(ID::Q))) + if (bit.wire && design->selected(module, bit.wire)) + wire_selected = true; + if (!cell_selected && !wire_selected) + continue; + for (auto bit : sigmap(cell->getPort(ID::Q))) ffbits.insert(bit); } diff --git a/tests/various/setundef_selection.ys b/tests/various/setundef_selection.ys index 67df8bed9..64713a742 100644 --- a/tests/various/setundef_selection.ys +++ b/tests/various/setundef_selection.ys @@ -7,21 +7,26 @@ endmodule EOT setundef -zero w:a sat -prove a 0 +sat -enable_undef -prove b 0 -falsify design -reset # Test that setundef -undriven -zero respects wire selection -read_verilog < Date: Sun, 8 Mar 2026 20:14:03 -0400 Subject: [PATCH 9/9] changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change --- tests/various/setundef_selection.ys | 2 +- tests/various/setundef_selection_undriven.il | 4 ---- tests/various/setundef_selection_undriven.v | 4 ++++ 3 files changed, 5 insertions(+), 5 deletions(-) delete mode 100644 tests/various/setundef_selection_undriven.il create mode 100644 tests/various/setundef_selection_undriven.v diff --git a/tests/various/setundef_selection.ys b/tests/various/setundef_selection.ys index 64713a742..c49cc06da 100644 --- a/tests/various/setundef_selection.ys +++ b/tests/various/setundef_selection.ys @@ -11,7 +11,7 @@ sat -enable_undef -prove b 0 -falsify design -reset # Test that setundef -undriven -zero respects wire selection -read_rtlil setundef_selection_undriven.il +read_verilog setundef_selection_undriven.v setundef -undriven -zero w:b sat -prove b 0 sat -enable_undef -prove a 0 -falsify diff --git a/tests/various/setundef_selection_undriven.il b/tests/various/setundef_selection_undriven.il deleted file mode 100644 index f77809eb2..000000000 --- a/tests/various/setundef_selection_undriven.il +++ /dev/null @@ -1,4 +0,0 @@ -module \test - wire output 1 \a - wire output 2 \b -end diff --git a/tests/various/setundef_selection_undriven.v b/tests/various/setundef_selection_undriven.v new file mode 100644 index 000000000..1fe5d585a --- /dev/null +++ b/tests/various/setundef_selection_undriven.v @@ -0,0 +1,4 @@ +module test; + wire a; + wire b; +endmodule