diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 5d2ccfcc8..99a223bdc 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -310,6 +310,8 @@ struct SetundefPass : public Pass {
 
 					RTLIL::SigSpec sig = undriven_signals.export_all();
 					for (auto &c : sig.chunks()) {
+						if (!design->selected(module, c.wire))
+							continue;
 						RTLIL::Wire * wire;
 						if (c.wire->width == c.width) {
 							wire = c.wire;
@@ -328,12 +330,12 @@ struct SetundefPass : public Pass {
 					SigMap sigmap(module);
 					SigPool undriven_signals;
 
-					for (auto &it : module->wires_)
-						undriven_signals.add(sigmap(it.second));
+					for (auto wire : module->selected_wires())
+						undriven_signals.add(sigmap(wire));
 
-					for (auto &it : module->wires_)
-						if (it.second->port_input)
-							undriven_signals.del(sigmap(it.second));
+					for (auto wire : module->selected_wires())
+						if (wire->port_input)
+							undriven_signals.del(sigmap(wire));
 
 					CellTypes ct(design);
 					for (auto &it : module->cells_)
@@ -367,6 +369,14 @@ struct SetundefPass : public Pass {
 					if (!cell->is_builtin_ff())
 						continue;
 
+					bool cell_selected = design->selected(module, cell);
+   	 			bool wire_selected = false;
+					for (auto bit : sigmap(cell->getPort(ID::Q)))
+						if (bit.wire && design->selected(module, bit.wire))
+							wire_selected = true;
+					if (!cell_selected && !wire_selected)
+						continue;
+
 					for (auto bit : sigmap(cell->getPort(ID::Q)))
 						ffbits.insert(bit);
 				}
@@ -502,14 +512,21 @@ struct SetundefPass : public Pass {
 				}
 			}
 
-			for (auto &it : module->cells_)
-				if (!it.second->get_bool_attribute(ID::xprop_decoder))
-					it.second->rewrite_sigspecs(worker);
-			for (auto &it : module->processes)
-				it.second->rewrite_sigspecs(worker);
+			for (auto cell : module->selected_cells())
+				if (!cell->get_bool_attribute(ID::xprop_decoder))
+					cell->rewrite_sigspecs(worker);
+			for (auto proc : module->selected_processes())
+				proc->rewrite_sigspecs(worker);
 			for (auto &it : module->connections_) {
-				worker(it.first);
-				worker(it.second);
+				SigSpec lhs = it.first;
+				bool selected = false;
+				for (auto &chunk : lhs.chunks())
+					if (chunk.wire && module->design->selected(module, chunk.wire))
+						selected = true;
+				if (selected) {
+					worker(it.first);
+					worker(it.second);
+				}
 			}
 
 			if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)
diff --git a/tests/various/setundef_selection.ys b/tests/various/setundef_selection.ys
new file mode 100644
index 000000000..c49cc06da
--- /dev/null
+++ b/tests/various/setundef_selection.ys
@@ -0,0 +1,32 @@
+# Test that setundef -zero respects wire selection: only selected wire is changed
+read_verilog <<EOT
+module test;
+    wire a = 1'bx;
+    wire b = 1'bx;
+endmodule
+EOT
+setundef -zero w:a
+sat -prove a 0
+sat -enable_undef -prove b 0 -falsify
+design -reset
+
+# Test that setundef -undriven -zero respects wire selection
+read_verilog setundef_selection_undriven.v
+setundef -undriven -zero w:b
+sat -prove b 0
+sat -enable_undef -prove a 0 -falsify
+design -reset
+
+# Test that setundef -init respects cell selection: only selected FF gets init set
+read_rtlil setundef_selection_ff.il
+setundef -init -zero c:myff_a
+select -assert-count 1 w:* a:init %i
+select -assert-count 0 w:b a:init %i
+design -reset
+
+# Test that setundef -init works with wire selection
+read_rtlil setundef_selection_ff.il
+setundef -init -zero w:a
+select -assert-count 1 w:* a:init %i
+select -assert-count 0 w:b a:init %i
+design -reset
diff --git a/tests/various/setundef_selection_ff.il b/tests/various/setundef_selection_ff.il
new file mode 100644
index 000000000..c9d9cc450
--- /dev/null
+++ b/tests/various/setundef_selection_ff.il
@@ -0,0 +1,19 @@
+module \test
+  wire input 1 \clk
+  wire output 2 \a
+  wire output 3 \b
+  cell $dff \myff_a
+    parameter \WIDTH 1
+    parameter \CLK_POLARITY 1'1
+    connect \D \a
+    connect \Q \a
+    connect \CLK \clk
+  end
+  cell $dff \myff_b
+    parameter \WIDTH 1
+    parameter \CLK_POLARITY 1'1
+    connect \D \b
+    connect \Q \b
+    connect \CLK \clk
+  end
+end
diff --git a/tests/various/setundef_selection_undriven.v b/tests/various/setundef_selection_undriven.v
new file mode 100644
index 000000000..1fe5d585a
--- /dev/null
+++ b/tests/various/setundef_selection_undriven.v
@@ -0,0 +1,4 @@
+module test;
+    wire a;
+    wire b;
+endmodule