From 1dce798dc5050745490600c09c873d821548f4f7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 May 2020 16:39:16 -0700 Subject: [PATCH 1/4] tests: add ecp5 latch testcase with -abc9 --- tests/arch/ecp5/latches_abc9.ys | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 tests/arch/ecp5/latches_abc9.ys diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys new file mode 100644 index 000000000..ca3182254 --- /dev/null +++ b/tests/arch/ecp5/latches_abc9.ys @@ -0,0 +1,16 @@ +read_verilog < Date: Mon, 25 May 2020 16:40:30 -0700 Subject: [PATCH 2/4] xaiger: promote abc9_keep wires --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 6b910eecd..4a8f54c4d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -156,7 +156,7 @@ struct XAigerWriter // promote keep wires for (auto wire : module->wires()) - if (wire->get_bool_attribute(ID::keep)) + if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep)) sigmap.add(wire); for (auto wire : module->wires()) { From 00c5ceb1f2c28435fa245a5183d325c441b8e5eb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 May 2020 16:40:53 -0700 Subject: [PATCH 3/4] abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort --- passes/techmap/abc9_ops.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8d55b18a0..16b468b19 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff) bit_users[bit].insert(cell->name); if (cell->output(conn.first) && !abc9_flop) - for (auto bit : sigmap(conn.second)) - bit_drivers[bit].insert(cell->name); + for (const auto &chunk : conn.second.chunks()) + if (!chunk.wire->get_bool_attribute(ID::abc9_keep)) + for (auto b : sigmap(SigSpec(chunk))) + bit_drivers[b].insert(cell->name); } toposort.node(cell->name); } From 8a11019d382f3eb5a8d95ce64511a1dcbbe2acfe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 3 Jun 2020 08:41:55 -0700 Subject: [PATCH 4/4] tests: tidy up testcase --- tests/arch/ecp5/latches_abc9.ys | 3 --- 1 file changed, 3 deletions(-) diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys index ca3182254..4daf04050 100644 --- a/tests/arch/ecp5/latches_abc9.ys +++ b/tests/arch/ecp5/latches_abc9.ys @@ -7,9 +7,6 @@ always @* assign q = ~l; endmodule EOT -proc -design -save gold - # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -abc9 select -assert-count 2 t:LUT4