diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 6b910eecd..4a8f54c4d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -156,7 +156,7 @@ struct XAigerWriter
 
 		// promote keep wires
 		for (auto wire : module->wires())
-			if (wire->get_bool_attribute(ID::keep))
+			if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep))
 				sigmap.add(wire);
 
 		for (auto wire : module->wires()) {
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8d55b18a0..16b468b19 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 					bit_users[bit].insert(cell->name);
 
 			if (cell->output(conn.first) && !abc9_flop)
-				for (auto bit : sigmap(conn.second))
-					bit_drivers[bit].insert(cell->name);
+				for (const auto &chunk : conn.second.chunks())
+				    if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
+					    for (auto b : sigmap(SigSpec(chunk)))
+						    bit_drivers[b].insert(cell->name);
 		}
 		toposort.node(cell->name);
 	}
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
index 000000000..4daf04050
--- /dev/null
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+    if (e)
+        l = ~d;
+assign q = ~l;
+endmodule
+EOT
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D