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synth_gatemate: Initial implementation

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Signed-off-by: Patrick Urban <patrick.urban@web.de>
This commit is contained in:
Patrick Urban 2021-09-13 17:16:15 +02:00 • committed by Marcelina Kościelnicka
parent b3e2001e1f
commit 240d289fff
29 changed files with 4053 additions and 0 deletions
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16
techlibs/gatemate/Makefile.inc Normal file
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OBJS += techlibs/gatemate/synth_gatemate.o
OBJS += techlibs/gatemate/gatemate_bramopt.o
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/iob_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/reg_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mux_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/lut_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mul_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/arith_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/cells_sim.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/cells_bb.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams.txt))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_20.vh))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_40.vh))

69
techlibs/gatemate/arith_map.v Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1)
begin: slice
CC_ADDF addf_i (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.CO(CO[i]),
.S(Y[i])
);
end
endgenerate
assign X = AA ^ BB;
endmodule

280
techlibs/gatemate/brams.txt Normal file
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bram $__CC_BRAM_CASCADE
init 1
abits 16 @a16d1
dbits 1 @a16d1
groups 2
ports 1 1
wrmode 1 0
enable 1 1 @a16d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__CC_BRAM_40K_SDP
init 1
abits 9 @a9d80
dbits 80 @a9d80
groups 2
ports 1 1
wrmode 1 0
enable 80 1 @a9d80
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__CC_BRAM_20K_SDP
init 1
abits 9 @a9d40
dbits 40 @a9d40
groups 2
ports 1 1
wrmode 1 0
enable 40 1 @a9d40
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__CC_BRAM_40K_TDP
init 1
abits 10 @a10d40
dbits 40 @a10d40
abits 11 @a11d20
dbits 20 @a11d20
abits 12 @a12d10
dbits 10 @a12d10
abits 13 @a13d5
dbits 5 @a13d5
abits 14 @a14d2
dbits 2 @a14d2
abits 15 @a15d1
dbits 1 @a15d1
groups 2
ports 1 1
wrmode 1 0
enable 40 1 @a10d40
enable 20 1 @a11d20
enable 10 1 @a12d10
enable 5 1 @a13d5
enable 2 1 @a14d2
enable 1 1 @a15d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__CC_BRAM_20K_TDP
init 1
abits 10 @a10d20
dbits 20 @a10d20
abits 11 @a11d10
dbits 10 @a11d10
abits 12 @a12d5
dbits 5 @a12d5
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 1 0
enable 20 1 @a10d20
enable 10 1 @a11d10
enable 5 1 @a12d5
enable 2 1 @a13d2
enable 1 1 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__CC_BRAM_CASCADE
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_CASCADE
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_CASCADE
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_SDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_SDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_SDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_SDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_SDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_SDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_TDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_TDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_TDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_TDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_TDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_TDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
endmatch

64
techlibs/gatemate/brams_init_20.vh Normal file
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.INIT_00(permute_init(INIT[ 0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_01(permute_init(INIT[ 1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_02(permute_init(INIT[ 2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_03(permute_init(INIT[ 3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_04(permute_init(INIT[ 4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_05(permute_init(INIT[ 5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_06(permute_init(INIT[ 6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_07(permute_init(INIT[ 7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_08(permute_init(INIT[ 8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_09(permute_init(INIT[ 9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),

128
techlibs/gatemate/brams_init_40.vh Normal file
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@ -0,0 +1,128 @@
.INIT_00(permute_init(INIT[ 0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_01(permute_init(INIT[ 1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_02(permute_init(INIT[ 2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_03(permute_init(INIT[ 3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_04(permute_init(INIT[ 4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_05(permute_init(INIT[ 5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_06(permute_init(INIT[ 6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_07(permute_init(INIT[ 7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_08(permute_init(INIT[ 8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_09(permute_init(INIT[ 9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_40(permute_init(INIT[ 64*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_41(permute_init(INIT[ 65*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_42(permute_init(INIT[ 66*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_43(permute_init(INIT[ 67*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_44(permute_init(INIT[ 68*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_45(permute_init(INIT[ 69*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_46(permute_init(INIT[ 70*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_47(permute_init(INIT[ 71*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_48(permute_init(INIT[ 72*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_49(permute_init(INIT[ 73*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4A(permute_init(INIT[ 74*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4B(permute_init(INIT[ 75*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4C(permute_init(INIT[ 76*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4D(permute_init(INIT[ 77*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4E(permute_init(INIT[ 78*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_4F(permute_init(INIT[ 79*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_50(permute_init(INIT[ 80*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_51(permute_init(INIT[ 81*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_52(permute_init(INIT[ 82*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_53(permute_init(INIT[ 83*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_54(permute_init(INIT[ 84*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_55(permute_init(INIT[ 85*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_56(permute_init(INIT[ 86*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_57(permute_init(INIT[ 87*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_58(permute_init(INIT[ 88*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_59(permute_init(INIT[ 89*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5A(permute_init(INIT[ 90*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5B(permute_init(INIT[ 91*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5C(permute_init(INIT[ 92*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5D(permute_init(INIT[ 93*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5E(permute_init(INIT[ 94*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_5F(permute_init(INIT[ 95*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_60(permute_init(INIT[ 96*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_61(permute_init(INIT[ 97*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_62(permute_init(INIT[ 98*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_63(permute_init(INIT[ 99*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_64(permute_init(INIT[100*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_65(permute_init(INIT[101*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_66(permute_init(INIT[102*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_67(permute_init(INIT[103*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_68(permute_init(INIT[104*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_69(permute_init(INIT[105*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6A(permute_init(INIT[106*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6B(permute_init(INIT[107*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6C(permute_init(INIT[108*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6D(permute_init(INIT[109*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6E(permute_init(INIT[110*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_6F(permute_init(INIT[111*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_70(permute_init(INIT[112*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_71(permute_init(INIT[113*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_72(permute_init(INIT[114*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_73(permute_init(INIT[115*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_74(permute_init(INIT[116*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_75(permute_init(INIT[117*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_76(permute_init(INIT[118*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_77(permute_init(INIT[119*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_78(permute_init(INIT[120*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_79(permute_init(INIT[121*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7A(permute_init(INIT[122*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7B(permute_init(INIT[123*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7C(permute_init(INIT[124*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7D(permute_init(INIT[125*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7E(permute_init(INIT[126*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
.INIT_7F(permute_init(INIT[127*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),

539
techlibs/gatemate/brams_map.v Normal file
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@ -0,0 +1,539 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$__CC_BRAM_20K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 14;
parameter CFG_DBITS = 40;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
// 512 x 40 bit
parameter [20479:0] INIT = 20480'b0;
input CLK2;
input CLK3;
// write side of the memory
input [15:0] A1ADDR;
input [39:0] A1DATA;
input [39:0] A1EN;
// read side of the memory
input [15:0] B1ADDR;
output [39:0] B1DATA;
input [0:0] B1EN;
// unconnected signals
wire ECC_1B_ERR, ECC_2B_ERR;
// internal signals
wire [15:0] ADDRA = {A1ADDR, 7'b0};
wire [15:0] ADDRB = {B1ADDR, 7'b0};
localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
if (CFG_DBITS <= 2) begin
for (i = 0; i < 64; i = i + 1) begin
if (^chunk[i * 4 +: 4] === 1'bx) begin
permute_init[i * 5 +: 5] = 5'b0;
end
else begin
permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
end
end
end else begin
permute_init = chunk;
end
end
endfunction
CC_BRAM_20K #(
`include "brams_init_20.vh"
.LOC("UNPLACED"),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("SDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
.A_EN_INV(1'b0), .B_EN_INV(1'b0),
.A_WE_INV(1'b0), .B_WE_INV(1'b0),
.A_DO_REG(1'b0), .B_DO_REG(1'b0),
.ECC_EN(1'b0)
) _TECHMAP_REPLACE_ (
.A_DO(B1DATA[19:0]),
.B_DO(B1DATA[39:20]),
.ECC_1B_ERR(ECC_1B_ERR),
.ECC_2B_ERR(ECC_2B_ERR),
.A_CLK(CLK2),
.B_CLK(CLK3),
.A_EN(1'b1),
.B_EN(B1EN),
.A_WE(1'b1),
.B_WE(1'b0),
.A_ADDR(ADDRA),
.B_ADDR(ADDRB),
.A_DI(A1DATA[19:0]),
.B_DI(A1DATA[39:20]),
.A_BM(A1EN[19:0]),
.B_BM(A1EN[39:20])
);
endmodule
module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 15;
parameter CFG_DBITS = 80;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
// 512 x 80 bit
parameter [40959:0] INIT = 40960'b0;
input CLK2;
input CLK3;
// write side of the memory
input [15:0] A1ADDR;
input [79:0] A1DATA;
input [79:0] A1EN;
// read side of the memory
input [15:0] B1ADDR;
output [79:0] B1DATA;
input [0:0] B1EN;
// unconnected signals
wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;
// internal signals
wire [15:0] ADDRA = {A1ADDR, 7'b0};
wire [15:0] ADDRB = {B1ADDR, 7'b0};
localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
if (CFG_DBITS <= 2) begin
for (i = 0; i < 64; i = i + 1) begin
if (^chunk[i * 4 +: 4] === 1'bx) begin
permute_init[i * 5 +: 5] = 5'b0;
end
else begin
permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
end
end
end else begin
permute_init = chunk;
end
end
endfunction
CC_BRAM_40K #(
`include "brams_init_40.vh"
.LOC("UNPLACED"),
.CAS("NONE"),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("SDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
.A_EN_INV(1'b0), .B_EN_INV(1'b0),
.A_WE_INV(1'b0), .B_WE_INV(1'b0),
.A_DO_REG(1'b0), .B_DO_REG(1'b0),
.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
) _TECHMAP_REPLACE_ (
.A_DO(B1DATA[39:0]),
.B_DO(B1DATA[79:40]),
.A_ECC_1B_ERR(A_ECC_1B_ERR),
.B_ECC_1B_ERR(B_ECC_1B_ERR),
.A_ECC_2B_ERR(A_ECC_2B_ERR),
.B_ECC_2B_ERR(B_ECC_2B_ERR),
.A_CLK(CLK2),
.B_CLK(CLK3),
.A_EN(1'b1),
.B_EN(B1EN),
.A_WE(1'b1),
.B_WE(1'b0),
.A_ADDR(ADDRA),
.B_ADDR(ADDRB),
.A_DI(A1DATA[39:0]),
.B_DI(A1DATA[79:40]),
.A_BM(A1EN[39:0]),
.B_BM(A1EN[79:40])
);
endmodule
module \$__CC_BRAM_20K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 14;
parameter CFG_DBITS = 20;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
// 512 x 40 bit
parameter [20479:0] INIT = 20480'b0;
input CLK2;
input CLK3;
// write side of the memory
input [15:0] A1ADDR;
input [19:0] A1DATA;
input [19:0] A1EN;
// read side of the memory
input [15:0] B1ADDR;
output [19:0] B1DATA;
input [0:0] B1EN;
// unconnected signals
wire [19:0] A_DO;
wire ECC_1B_ERR, ECC_2B_ERR;
localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
if (CFG_DBITS <= 2) begin
for (i = 0; i < 64; i = i + 1) begin
if (^chunk[i * 4 +: 4] === 1'bx) begin
permute_init[i * 5 +: 5] = 5'b0;
end
else begin
permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
end
end
end else begin
permute_init = chunk;
end
end
endfunction
// internal signals
generate
wire [15:0] ADDRA;
wire [15:0] ADDRB;
if (CFG_DBITS == 1) begin: blk
assign ADDRA = {A1ADDR[13:5], 1'b0, A1ADDR[4:0], 1'b0};
assign ADDRB = {B1ADDR[13:5], 1'b0, B1ADDR[4:0], 1'b0};
end
else if (CFG_DBITS == 2) begin: blk
assign ADDRA = {A1ADDR[12:4], 1'b0, A1ADDR[3:0], 2'b0};
assign ADDRB = {B1ADDR[12:4], 1'b0, B1ADDR[3:0], 2'b0};
end
else if (CFG_DBITS == 5) begin: blk
assign ADDRA = {A1ADDR[11:3], 1'b0, A1ADDR[2:0], 3'b0};
assign ADDRB = {B1ADDR[11:3], 1'b0, B1ADDR[2:0], 3'b0};
end
else if (CFG_DBITS == 10) begin: blk
assign ADDRA = {A1ADDR[10:2], 1'b0, A1ADDR[1:0], 4'b0};
assign ADDRB = {B1ADDR[10:2], 1'b0, B1ADDR[1:0], 4'b0};
end
else if (CFG_DBITS == 20) begin: blk
assign ADDRA = {A1ADDR[9:1], 1'b0, A1ADDR[0], 5'b0};
assign ADDRB = {B1ADDR[9:1], 1'b0, B1ADDR[0], 5'b0};
end
CC_BRAM_20K #(
`include "brams_init_20.vh"
.LOC("UNPLACED"),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
.A_EN_INV(1'b0), .B_EN_INV(1'b0),
.A_WE_INV(1'b0), .B_WE_INV(1'b0),
.A_DO_REG(1'b0), .B_DO_REG(1'b0),
.ECC_EN(1'b0)
) _TECHMAP_REPLACE_ (
.A_DO(A_DO),
.B_DO(B1DATA),
.ECC_1B_ERR(ECC_1B_ERR),
.ECC_2B_ERR(ECC_2B_ERR),
.A_CLK(CLK2),
.B_CLK(CLK3),
.A_EN(1'b1),
.B_EN(B1EN),
.A_WE(1'b1),
.B_WE(1'b0),
.A_ADDR(ADDRA),
.B_ADDR(ADDRB),
.A_DI(A1DATA),
.B_DI(20'b0),
.A_BM(A1EN),
.B_BM(20'b0)
);
endgenerate
endmodule
module \$__CC_BRAM_40K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 15;
parameter CFG_DBITS = 40;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
// 512 x 80 bit
parameter [40959:0] INIT = 40960'b0;
input CLK2;
input CLK3;
// write side of the memory
input [15:0] A1ADDR;
input [39:0] A1DATA;
input [39:0] A1EN;
// read side of the memory
input [15:0] B1ADDR;
output [39:0] B1DATA;
input [0:0] B1EN;
// unconnected signals
wire [39:0] A_DO;
wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;
localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
if (CFG_DBITS <= 2) begin
for (i = 0; i < 64; i = i + 1) begin
permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]} & 5'b11111;
end
end else begin
permute_init = chunk;
end
end
endfunction
generate
wire [15:0] ADDRA;
wire [15:0] ADDRB;
if (CFG_DBITS == 1) begin
assign ADDRA = {A1ADDR, 1'b0};
assign ADDRB = {B1ADDR, 1'b0};
end
else if (CFG_DBITS == 2) begin
assign ADDRA = {A1ADDR, 2'b0};
assign ADDRB = {B1ADDR, 2'b0};
end
else if (CFG_DBITS == 5) begin
assign ADDRA = {A1ADDR, 3'b0};
assign ADDRB = {B1ADDR, 3'b0};
end
else if (CFG_DBITS == 10) begin
assign ADDRA = {A1ADDR, 4'b0};
assign ADDRB = {B1ADDR, 4'b0};
end
else if (CFG_DBITS == 20) begin
assign ADDRA = {A1ADDR, 5'b0};
assign ADDRB = {B1ADDR, 5'b0};
end
else if (CFG_DBITS == 40) begin
assign ADDRA = {A1ADDR, 6'b0};
assign ADDRB = {B1ADDR, 6'b0};
end
CC_BRAM_40K #(
`include "brams_init_40.vh"
.LOC("UNPLACED"),
.CAS("NONE"),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
.A_EN_INV(1'b0), .B_EN_INV(1'b0),
.A_WE_INV(1'b0), .B_WE_INV(1'b0),
.A_DO_REG(1'b0), .B_DO_REG(1'b0),
.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
) _TECHMAP_REPLACE_ (
.A_DO(A_DO),
.B_DO(B1DATA),
.A_ECC_1B_ERR(A_ECC_1B_ERR),
.B_ECC_1B_ERR(B_ECC_1B_ERR),
.A_ECC_2B_ERR(A_ECC_2B_ERR),
.B_ECC_2B_ERR(B_ECC_2B_ERR),
.A_CLK(CLK2),
.B_CLK(CLK3),
.A_EN(1'b1),
.B_EN(B1EN),
.A_WE(1'b1),
.B_WE(1'b0),
.A_ADDR(ADDRA),
.B_ADDR(ADDRB),
.A_DI(A1DATA),
.B_DI(40'b0),
.A_BM(A1EN),
.B_BM(40'b0)
);
endgenerate
endmodule
module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 16;
parameter CFG_DBITS = 1;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
// 64K x 1
parameter [65535:0] INIT = 65535'b0;
input CLK2;
input CLK3;
// write side of the memory
input [15:0] A1ADDR;
input [39:0] A1DATA;
input [39:0] A1EN;
// read side of the memory
input [15:0] B1ADDR;
output [39:0] B1DATA;
input [0:0] B1EN;
// cascade signals
wire A_CAS, B_CAS;
// unconnected signals
wire [39:0] A_UP_DO, A_LO_DO, B_LO_DO;
wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;
localparam INIT_CHUNK_SIZE = 256;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
for (i = 0; i < 64; i = i + 1) begin
permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]} & 5'b11111;
end
end
endfunction
generate
CC_BRAM_40K #(
`include "brams_init_40.vh"
.LOC("UNPLACED"),
.CAS("UPPER"),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
.A_EN_INV(1'b0), .B_EN_INV(1'b0),
.A_WE_INV(1'b0), .B_WE_INV(1'b0),
.A_DO_REG(1'b0), .B_DO_REG(1'b0),
.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
) upper_cell (
.A_CI(A_CAS),
.B_CI(B_CAS),
.A_DO(A_UP_DO),
.B_DO(B1DATA),
.A_ECC_1B_ERR(A_ECC_1B_ERR),
.B_ECC_1B_ERR(B_ECC_1B_ERR),
.A_ECC_2B_ERR(A_ECC_2B_ERR),
.B_ECC_2B_ERR(B_ECC_2B_ERR),
.A_CLK(CLK2),
.B_CLK(CLK3),
.A_EN(1'b1),
.B_EN(B1EN),
.A_WE(1'b1),
.B_WE(1'b0),
.A_ADDR(A1ADDR),
.B_ADDR(B1ADDR),
.A_DI(A1DATA),
.B_DI(40'b0),
.A_BM(A1EN),
.B_BM(40'b0)
);
CC_BRAM_40K #(
`include "brams_init_40.vh"
.LOC("UNPLACED"),
.CAS("LOWER"),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
.A_EN_INV(1'b0), .B_EN_INV(1'b0),
.A_WE_INV(1'b0), .B_WE_INV(1'b0),
.A_DO_REG(1'b0), .B_DO_REG(1'b0),
.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
) lower_cell (
.A_CI(1'b1),
.B_CI(),
.A_CO(A_CAS),
.B_CO(B_CAS),
.A_CLK(CLK2),
.B_CLK(CLK3),
.A_EN(1'b1),
.B_EN(B1EN),
.A_WE(1'b1),
.B_WE(1'b0),
.A_ADDR(A1ADDR),
.B_ADDR(B1ADDR),
.A_DI(A1DATA),
.B_DI(40'b0),
.A_BM(A1EN),
.B_BM(40'b0)
);
endgenerate
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_SERDES #(
parameter SERDES_CFG = ""
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWERDOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input CLK_CORE_TX_I,
input CLK_CORE_RX_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWERDOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input CLK_REG_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output RX_DETECT_DONE_O,
output RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESETDONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESETDONE_O,
output RX_EI_EN_O,
output CLK_CORE_RX_O,
output CLK_CORE_PLL_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
bool binary_pred(SigBit s1, SigBit s2)
{
return s1 == s2;
}
static void proc_glwren(Module *module)
{
std::vector<Cell*> ram_cells;
// Gather RAM cells
for (auto cell : module->cells())
{
if (cell->type.in(ID(CC_DPSRAM_20K), ID(CC_DPSRAM_40K))) {
ram_cells.push_back(cell);
}
}
// Convert bitmask signals
for (auto cell : ram_cells)
{
std::vector<SigBit> mska = cell->getPort(ID(A_BM)).to_sigbit_vector();
std::vector<SigBit> mskb = cell->getPort(ID(B_BM)).to_sigbit_vector();
// Remove State::S0 from vectors
mska.erase(std::remove_if(mska.begin(), mska.end(), [](const SigBit & sb){return (sb == State::S0);}), mska.end());
mskb.erase(std::remove_if(mskb.begin(), mskb.end(), [](const SigBit & sb){return (sb == State::S0);}), mskb.end());
if (mska.size() + mskb.size() == 0) {
break;
}
if (cell->getParam(ID(RAM_MODE)).decode_string() == "SDP")
{
std::vector<SigBit> msk;
msk.insert(msk.end(), mska.begin(), mska.end());
msk.insert(msk.end(), mskb.begin(), mskb.end());
if (std::equal(msk.begin() + 1, msk.end(), msk.begin(), binary_pred))
{
if ((cell->getPort(ID(A_WE)) == State::S1) && (cell->getPort(ID(B_WE)) == State::S0))
{
cell->setPort(ID(A_WE), msk[0]);
cell->setPort(ID(B_WE), Const(0, 1));
// Set bitmask bits to _1_
cell->setPort(ID(A_BM), Const(State::S1, mska.size()));
cell->setPort(ID(B_BM), Const(State::S1, mskb.size()));
}
}
}
else // RAM_MODE == "TDP"
{
if (std::equal(mska.begin() + 1, mska.end(), mska.begin(), binary_pred))
{
if (cell->getPort(ID(A_WE)) == State::S1)
{
// Signals are all equal
cell->setPort(ID(A_WE), mska[0]);
cell->setPort(ID(A_BM), Const(State::S1, mska.size()));
}
}
if (std::equal(mskb.begin() + 1, mskb.end(), mskb.begin(), binary_pred))
{
if (cell->getPort(ID(B_WE)) == State::S1)
{
cell->setPort(ID(B_WE), mskb[0]);
// Set bitmask bits to _1_
cell->setPort(ID(B_BM), Const(State::S1, mskb.size()));
}
}
}
}
}
struct GateMateBramOptPass : public Pass {
GateMateBramOptPass() : Pass("gatemate_bramopt", "GateMate: optimize block RAM cells") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" gatemate_bramopt [options] [selection]\n");
log("\n");
log("This pass processes all CC_BRAM_20K and CC_BRAM_40K cells and tries to");
log("convert its enable bitmask wires to a single global enable signal.");
log("\n");
log(" -noglwren\n");
log(" do not convert bitmasks to single global write enable signals.\n");
log("\n");
}
bool noglwren;
void clear_flags() override
{
noglwren = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing GATEMATE_BRAMOPT pass (optimize block RAM).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-noglwren") {
noglwren = true;
continue;
}
break;
}
extra_args(args, argidx, design);
Module *module = design->top_module();
if (module == nullptr)
{
log_cmd_error("No top module found.\n");
}
if (!noglwren) {
proc_glwren(module);
}
}
} GateMateBramOptPass;
PRIVATE_NAMESPACE_END

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$__inpad (input I, output Y);
CC_IBUF /*#(
.PIN_NAME("UNPLACED"),
.V_IO("UNDEFINED"),
.PULLUP(1'bx),
.PULLDOWN(1'bx),
.KEEPER(1'bx),
.SCHMITT_TRIGGER(1'bx),
.DELAY_IBF(4'bx),
.FF_IBF(1'bx)
)*/ _TECHMAP_REPLACE_ (
.I(I),
.Y(Y)
);
endmodule
module \$__outpad (input A, output O);
CC_OBUF /*#(
.PIN_NAME("UNPLACED"),
.V_IO("UNDEFINED"),
.SLEW("UNDEFINED"),
.DRIVE(1'bx),
.DELAY_OBF(4'bx),
.FF_OBF(1'bx)
)*/ _TECHMAP_REPLACE_ (
.A(A),
.O(O)
);
endmodule
module \$__toutpad (input A, input OE, output O);
CC_TOBUF /*#(
.PIN_NAME("UNPLACED"),
.V_IO("UNDEFINED"),
.SLEW("UNDEFINED"),
.DRIVE(1'bx),
.PULLUP(1'bx),
.PULLDOWN(1'bx),
.KEEPER(1'bx),
.DELAY_OBF(4'bx),
.FF_OBF(1'bx)
)*/ _TECHMAP_REPLACE_ (
.A(A),
.T(~OE),
.O(O)
);
endmodule
module \$__tinoutpad (input A, input OE, inout IO, output Y);
CC_IOBUF /*#(
.PIN_NAME("UNPLACED"),
.V_IO("UNDEFINED"),
.SLEW("UNDEFINED"),
.DRIVE(1'bx),
.PULLUP(1'bx),
.PULLDOWN(1'bx),
.KEEPER(1'bx),
.SCHMITT_TRIGGER(1'bx),
.DELAY_IBF(4'bx),
.DELAY_OBF(4'bx),
.FF_IBF(1'bx),
.FF_OBF(1'bx)
)*/ _TECHMAP_REPLACE_ (
.A(A),
.T(~OE),
.IO(IO),
.Y(Y)
);
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`define MAX(a,b) (a > b ? a : b)
`define MIN(a,b) (a < b ? a : b)
(* techmap_celltype = "$mul $__mul" *)
module \$__MULMXN (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
localparam MAXWIDTH = `MAX(A_WIDTH, B_WIDTH) + ((A_SIGNED || B_SIGNED) ? 0 : 1);
generate
if (A_SIGNED) begin: blkA
wire signed [MAXWIDTH-1:0] Aext = $signed(A);
end
else begin: blkA
wire [MAXWIDTH-1:0] Aext = A;
end
if (B_SIGNED) begin: blkB
wire signed [MAXWIDTH-1:0] Bext = $signed(B);
end
else begin: blkB
wire [MAXWIDTH-1:0] Bext = B;
end
if (A_WIDTH >= B_WIDTH) begin
CC_MULT #(
.A_WIDTH(MAXWIDTH),
.B_WIDTH(MAXWIDTH),
.P_WIDTH(`MIN(Y_WIDTH,MAXWIDTH+MAXWIDTH)),
) _TECHMAP_REPLACE_ (
.A(blkA.Aext),
.B(blkB.Bext),
.P(Y)
);
end
else begin // swap A,B
CC_MULT #(
.A_WIDTH(MAXWIDTH),
.B_WIDTH(MAXWIDTH),
.P_WIDTH(`MIN(Y_WIDTH,MAXWIDTH+MAXWIDTH)),
) _TECHMAP_REPLACE_ (
.A(blkB.Bext),
.B(blkA.Aext),
.P(Y)
);
end
endgenerate
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
CC_MX8 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.D4(E), .D5(F), .D6(G), .D7(H),
.S0(S), .S1(T), .S2(U),
.Y(Y)
);
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
CC_MX4 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.S0(S), .S1(T),
.Y(Y)
);
endmodule
/*
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(S),
.Y(Y)
);
endmodule
*/

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$_DFF_[NP]_" *)
module \$_DFF_x_ (input D, C, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DFF #(
.CLK_INV((_TECHMAP_CELLTYPE_[15:8] == "N")),
.EN_INV(1'b0),
.SR_INV(1'b0),
.SR_VAL(1'b0)
) _TECHMAP_REPLACE_ (.D(D), .EN(1'b1), .CLK(C), .SR(1'b0), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_DFF_[NP][NP][01]_" *)
module \$_DFF_xxx_ (input D, C, R, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.EN_INV(1'b0),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
) _TECHMAP_REPLACE_ (.D(D), .EN(1'b1), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_DFFE_[NP][NP]_" *)
module \$_DFFE_xx_ (input D, C, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(1'b0),
.SR_VAL(1'b0)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(1'b0), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1")
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP]_" *)
module \$_DLATCH_x_ (input E, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(1'b0),
.SR_VAL(1'b0)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(1'b0), .Q(Q));
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthGateMatePass : public ScriptPass
{
SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_gatemate [options]\n");
log("\n");
log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module.\n");
log("\n");
log(" -vlog <file>\n");
log(" write the design to the specified verilog file. Writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -blif <file>\n");
log(" write the design to the specified BLIF file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -edif <file>\n");
log(" write the design to the specified EDIF file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). An empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis.\n");
log("\n");
log(" -nobram\n");
log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
log("\n");
log(" -noaddf\n");
log(" do not use CC_ADDF full adder cells in output netlist.\n");
log("\n");
log(" -nomult\n");
log(" do not use CC_MULT multiplier cells in output netlist.\n");
log("\n");
log(" -nomx8, -nomx4\n");
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
log("\n");;
log(" -dff\n");
log(" run 'abc'/'abc9' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion.\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, vlog_file, blif_file, edif_file, json_file;
bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, dff, retime, noiopad, noclkbuf;
void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
blif_file = "";
edif_file = "";
json_file = "";
noflatten = false;
nobram = false;
noaddf = false;
nomult = false;
nomx4 = false;
nomx8 = false;
dff = false;
retime = false;
noiopad = false;
noclkbuf = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
vlog_file = args[++argidx];
continue;
}
if (args[argidx] == "-blif" && argidx+1 < args.size()) {
blif_file = args[++argidx];
continue;
}
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
edif_file = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
noflatten = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-noaddf") {
noaddf = true;
continue;
}
if (args[argidx] == "-nomult") {
nomult = true;
continue;
}
if (args[argidx] == "-nomx4") {
nomx4 = true;
continue;
}
if (args[argidx] == "-nomx8") {
nomx8 = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection()) {
log_cmd_error("This command only operates on fully selected designs!\n");
}
log_header(design, "Executing SYNTH_GATEMATE pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (check_label("prepare"))
{
run("proc");
if (!noflatten) {
run("flatten");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
run("share");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
}
if (check_label("map_mult", "(skip if '-nomult')"))
{
if (!nomult) {
run("techmap -map +/gatemate/mul_map.v");
}
}
if (check_label("coarse"))
{
run("alumacc");
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (check_label("map_bram", "(skip if '-nobram')"))
{
if (!nobram) {
run("memory_bram -rules +/gatemate/brams.txt");
run("setundef -zero -params "
"t:$__CC_BRAM_CASCADE "
"t:$__CC_BRAM_40K_SDP t:$__CC_BRAM_20K_SDP "
"t:$__CC_BRAM_20K_TDP t:$__CC_BRAM_40K_TDP "
);
run("techmap -map +/gatemate/brams_map.v");
run("gatemate_bramopt");
}
}
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_addf", "(skip if '-noaddf')"))
{
std::string techmap_args = "";
if (!noaddf) {
techmap_args += " -map +/gatemate/arith_map.v";
}
run("techmap -map +/techmap.v " + techmap_args);
run("opt -fast");
if (retime) {
run("abc -dff -D 1", "(only if -retime)");
}
}
if (check_label("map_io", "(skip if '-noiopad')"))
{
if (!noiopad) {
run("iopadmap -bits "
"-inpad $__inpad Y:I "
"-outpad $__outpad A:O "
"-toutpad $__toutpad OE:A:O "
"-tinoutpad $__tinoutpad OE:Y:A:IO"
);
run("techmap -map +/gatemate/iob_map.v");
run("clean");
}
}
if (check_label("map_regs"))
{
run("opt_clean");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFF_???_ 0 "
"-cell $_DFFE_??_ 0 -cell $_DFFE_????_ 0 "
"-cell $_DLATCH_?_ x -cell $_DLATCH_???_ x"
);
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("opt_clean");
}
if (check_label("map_muxs"))
{
run("abc -g simple"); // optimize design before muxcover
std::string muxcover_args;
if (!nomx4) {
muxcover_args += stringf(" -mux4");
}
if (!nomx8) {
muxcover_args += stringf(" -mux8");
}
run("muxcover " + muxcover_args);
run("opt -full");
run("techmap -map +/gatemate/mux_map.v");
}
if (check_label("map_luts"))
{
std::string abc_args = " -dress -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args);
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/gatemate/lut_map.v");
run("clean");
}
if (check_label("map_bufg", "(skip if '-noclkbuf')"))
{
if (!noclkbuf) {
run("clkbufmap -buf CC_BUFG O:I");
run("clean");
}
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat -width");
run("check -noinit");
run("blackbox =A:whitebox");
}
if (check_label("vlog"))
{
run("opt_clean -purge");
if (!vlog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file.c_str()));
}
}
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode) {
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
}
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode) {
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
}
}
if (check_label("blif"))
{
if (!blif_file.empty() || help_mode) {
run(stringf("write_blif %s", edif_file.c_str()));
}
}
}
} SynthGateMatePass;
PRIVATE_NAMESPACE_END

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read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:CC_ADDF
select -assert-count 4 t:CC_LUT1
select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D

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read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-count 1 t:CC_LUT2
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-count 1 t:CC_LUT2
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D

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read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:CC_ADDF
select -assert-count 1 t:CC_BUFG
select -assert-count 8 t:CC_DFF
select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D

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read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D

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read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
async2sync
miter -equiv -make_assert -flatten gold gate miter
stat
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-count 3 t:CC_LUT2
select -assert-count 4 t:CC_LUT3
select -assert-count 8 t:CC_LUT4
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D

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read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_DLT
select -assert-none t:CC_DLT %% t:* %D
design -load read
hierarchy -top latchn
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_DLT
select -assert-none t:CC_DLT %% t:* %D
design -load read
hierarchy -top latchsr
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_DLT
select -assert-count 2 t:CC_LUT3
select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D

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read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_LUT1
select -assert-count 6 t:CC_LUT2
select -assert-count 2 t:CC_LUT4
select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D

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# 512 x 40 bit -> CC_BRAM_20K SDP RAM
read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_ram_sdp
synth_gatemate -top sync_ram_sdp -noiopad
cd sync_ram_sdp
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_20K
# 512 x 80 bit -> CC_BRAM_40K SDP RAM
design -reset
read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_ram_sdp
synth_gatemate -top sync_ram_sdp -noiopad
cd sync_ram_sdp
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_40K
# 512 x 40 bit -> CC_BRAM_20K SDP ROM
design -reset
read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_rom
synth_gatemate -top sync_rom -noiopad
cd sync_rom
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_20K
# 512 x 80 bit -> CC_BRAM_40K SDP ROM
design -reset
read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_rom
synth_gatemate -top sync_rom -noiopad
cd sync_rom
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_40K

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module mul_plain(a, b, p);
parameter M = 6;
parameter N = 6;
input wire [M-1:0] a;
input wire [N-1:0] b;
output wire [M+N-1:0] p;
assign p = a * b;
endmodule
module mul_signed_async (clk, rst, en, a, b, p);
parameter M = 8;
parameter N = 6;
input wire signed clk, rst, en;
input wire signed [M-1:0] a;
input wire signed [N-1:0] b;
output reg signed [M+N-1:0] p;
reg signed [M-1:0] a_reg;
reg signed [N-1:0] b_reg;
// signed M*N multiplier with
// - input and output pipeline registers
// - asynchronous reset (active high)
// - clock enable (active high)
always @(posedge clk or posedge rst)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule
module mul_unsigned_sync (clk, rst, en, a, b, p);
parameter M = 6;
parameter N = 3;
input wire clk, rst, en;
input wire [M-1:0] a;
input wire [N-1:0] b;
output reg [M+N-1:0] p;
reg [M-1:0] a_reg;
reg [N-1:0] b_reg;
// unsigned M*N multiplier with
// - input and output pipeline registers
// - synchronous reset (active high)
// - clock enable (active high)
always @(posedge clk)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule

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read_verilog mul.v
design -save read
hierarchy -top mul_plain
proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_plain # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MULT
select -assert-none t:CC_MULT %% t:* %D
design -load read
hierarchy -top mul_signed_async
proc
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_signed_async # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MULT
select -assert-count 1 t:CC_BUFG
select -assert-count 28 t:CC_DFF
select -assert-none t:CC_MULT t:CC_BUFG t:CC_DFF %% t:* %D
design -load read
hierarchy -top mul_unsigned_sync
proc
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned_sync # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MULT
select -assert-count 1 t:CC_BUFG
select -assert-count 18 t:CC_LUT4
select -assert-count 18 t:CC_DFF
select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D

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tests/arch/gatemate/mux.ys Normal file
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read_verilog ../common/mux.v
design -save read
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MX4
select -assert-none t:CC_MX4 %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MX8
select -assert-none t:CC_MX8 %% t:* %D

4
tests/arch/gatemate/run-test.sh Executable file
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#!/usr/bin/env bash
set -eu
source ../../gen-tests-makefile.sh
run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

10
tests/arch/gatemate/shifter.ys Normal file
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read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 8 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D

13
tests/arch/gatemate/tribuf.ys Normal file
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read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 2 t:CC_IBUF
select -assert-count 1 t:CC_LUT1
select -assert-count 1 t:CC_TOBUF
select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D