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13 lines
484 B
Plaintext
13 lines
484 B
Plaintext
read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:CC_ADDF
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select -assert-count 1 t:CC_BUFG
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select -assert-count 8 t:CC_DFF
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select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D
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