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21 lines
777 B
Plaintext
21 lines
777 B
Plaintext
read_verilog ../common/mux.v
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design -save read
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_MX4
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select -assert-none t:CC_MX4 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_MX8
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select -assert-none t:CC_MX8 %% t:* %D
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