mirror of
https://github.com/YosysHQ/yosys
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89 lines
2.1 KiB
Verilog
89 lines
2.1 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module \$__inpad (input I, output Y);
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CC_IBUF /*#(
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.PIN_NAME("UNPLACED"),
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.V_IO("UNDEFINED"),
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.PULLUP(1'bx),
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.PULLDOWN(1'bx),
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.KEEPER(1'bx),
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.SCHMITT_TRIGGER(1'bx),
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.DELAY_IBF(4'bx),
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.FF_IBF(1'bx)
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)*/ _TECHMAP_REPLACE_ (
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.I(I),
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.Y(Y)
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);
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endmodule
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module \$__outpad (input A, output O);
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CC_OBUF /*#(
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.PIN_NAME("UNPLACED"),
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.V_IO("UNDEFINED"),
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.SLEW("UNDEFINED"),
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.DRIVE(1'bx),
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.DELAY_OBF(4'bx),
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.FF_OBF(1'bx)
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)*/ _TECHMAP_REPLACE_ (
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.A(A),
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.O(O)
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);
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endmodule
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module \$__toutpad (input A, input OE, output O);
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CC_TOBUF /*#(
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.PIN_NAME("UNPLACED"),
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.V_IO("UNDEFINED"),
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.SLEW("UNDEFINED"),
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.DRIVE(1'bx),
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.PULLUP(1'bx),
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.PULLDOWN(1'bx),
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.KEEPER(1'bx),
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.DELAY_OBF(4'bx),
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.FF_OBF(1'bx)
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)*/ _TECHMAP_REPLACE_ (
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.A(A),
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.T(~OE),
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.O(O)
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);
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endmodule
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module \$__tinoutpad (input A, input OE, inout IO, output Y);
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CC_IOBUF /*#(
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.PIN_NAME("UNPLACED"),
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.V_IO("UNDEFINED"),
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.SLEW("UNDEFINED"),
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.DRIVE(1'bx),
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.PULLUP(1'bx),
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.PULLDOWN(1'bx),
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.KEEPER(1'bx),
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.SCHMITT_TRIGGER(1'bx),
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.DELAY_IBF(4'bx),
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.DELAY_OBF(4'bx),
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.FF_IBF(1'bx),
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.FF_OBF(1'bx)
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)*/ _TECHMAP_REPLACE_ (
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.A(A),
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.T(~OE),
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.IO(IO),
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.Y(Y)
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);
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endmodule
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