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Jannis Harder c5dce57067 append_assume: Make append_assume on the default for now
Having `append_assume off` needs `vcd_sim on` to not be ignored with a
warning and `vcd_sim off` is still the default.
2023-02-08 14:18:52 +01:00
.github/workflows Update CI script 2022-10-24 08:31:45 +02:00
docs append_assume: Make append_assume on the default for now 2023-02-08 14:18:52 +01:00
extern Fixed names and links 2021-10-31 14:42:39 +01:00
sbysrc append_assume: Make append_assume on the default for now 2023-02-08 14:18:52 +01:00
tests Unified trace generation using yosys's sim across all engines 2023-01-10 18:42:26 +01:00
.gitignore Add aiger engine 2017-02-19 23:53:01 +01:00
.readthedocs.yaml update docs theme 2021-11-26 20:34:55 +01:00
COPYING Fixed names and links 2021-10-31 14:42:39 +01:00
Makefile Use the test Makefile for all examples 2022-06-13 13:42:58 +02:00
README.md mention tabby+oss cad suite in readme 2022-01-04 16:32:59 +01:00

SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See https://yosyshq.readthedocs.io/projects/sby/ for documentation on how to use SymbiYosys.

SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.


SymbiYosys (sby) is part of the Tabby CAD Suite and the OSS CAD Suite! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.

Make sure to get a Tabby CAD Suite Evaluation License for extensive SystemVerilog Assertion (SVA) support, as well as industry-grade SystemVerilog and VHDL parsers!

For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet.