Jannis Harder c5dce57067 append_assume: Make append_assume on the default for now ... Having `append_assume off` needs `vcd_sim on` to not be ignored with a warning and `vcd_sim off` is still the default.		2023-02-08 14:18:52 +01:00
..
sby.py	Add colors to early and late log messages	2022-11-02 12:35:11 +01:00
sby_autotune.py	Run tasks in parallel	2022-08-18 14:38:40 +02:00
sby_core.py	append_assume: Make append_assume on the default for now	2023-02-08 14:18:52 +01:00
sby_design.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_engine_abc.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_engine_aiger.py	avy: Fold aiger model using abc to support assumptions	2023-01-11 18:36:06 +01:00
sby_engine_btor.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_engine_smtbmc.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_jobserver.py	Support "fifo:" make jobserver auth	2023-01-10 18:42:26 +01:00
sby_mode_bmc.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_mode_cover.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_mode_live.py	Add colors to engine header message	2022-11-24 18:12:22 +01:00
sby_mode_prove.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_sim.py	Enable yosys sim support for clock signals in hierarchical designs	2023-01-11 18:02:45 +01:00