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George Rennie ff98e51c13
Merge pull request #317 from SeddonShen/main
feat(sby_engine_aiger): add rIC3 support for BMC mode
2025-03-26 10:17:15 +01:00
.github enable extensions 2024-10-16 17:14:42 +02:00
docs Merge pull request #313 from gipsyh/rIC3 2025-03-14 15:13:06 +01:00
extern Fixed names and links 2021-10-31 14:42:39 +01:00
sbysrc feat(sby_engine_aiger): add rIC3 support for BMC mode 2025-03-18 16:06:16 +08:00
tests add non-verific name mangling regression test 2024-10-16 15:05:02 +02:00
tools Replace (read_)ilang with (read_)rtlil 2024-11-05 12:55:09 +13:00
.gitattributes Add --version option based on git describe 2024-07-08 18:39:23 +02:00
.gitignore Add aiger engine 2017-02-19 23:53:01 +01:00
.gittag Add --version option based on git describe 2024-07-08 18:39:23 +02:00
.readthedocs.yaml Update .readthedocs.yaml 2023-05-08 11:33:14 +02:00
COPYING Fixed names and links 2021-10-31 14:42:39 +01:00
Makefile Add --version option based on git describe 2024-07-08 18:39:23 +02:00
README.md mention tabby+oss cad suite in readme 2022-01-04 16:32:59 +01:00

SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See https://yosyshq.readthedocs.io/projects/sby/ for documentation on how to use SymbiYosys.

SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.


SymbiYosys (sby) is part of the Tabby CAD Suite and the OSS CAD Suite! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.

Make sure to get a Tabby CAD Suite Evaluation License for extensive SystemVerilog Assertion (SVA) support, as well as industry-grade SystemVerilog and VHDL parsers!

For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet.