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125 lines
4.1 KiB
Markdown
125 lines
4.1 KiB
Markdown
Proving and Using Inductive Invariants for Interval Property Checking
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=====================================================================
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Inductive invariants are boolean functions over the design state, that
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1. return true for every reachable state (=invariants), and
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2. if they return true for a state then they will also return true
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for every state reachable from the given state (=inductive)
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Formally, inductive invariants are sets of states that are closed under
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the state transition function (=inductive), and contain the entire set
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of reachable states (=invariants).
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A user-friendly set of features to support Inductive Invariants (and Interval
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Property Checking) is in development. Until this is completed we recommend
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the following technique for proving and using inductive invariants.
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Consider the following circuit (stripped-down [example.sv](example.sv)):
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```SystemVerilog
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module example(clk, state);
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input logic clk;
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output logic [4:0] state = 27;
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always_ff @(posedge clk) state <= (5'd 2 * state - 5'd 1) ^ (state & 5'd 7);
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always_comb assert (state != 0);
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endmodule
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```
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For better understanding of this circuit we provide the complete state graph
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for that example design (as generated by [example.py](example.py)):
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```
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The 5-bit function f(x) produces 2 loops:
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f = lambda x: (2*x-1) ^ (x&7)
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4-Element Loop:
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31 ->- 26 ->- 17 ->- 0 ->- 31
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8 Lead-Ins:
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0 -<- 1 -<- 2
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`<- 18
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17 -<- 10 -<- 7
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`<- 23
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26 -<- 15 -<- 8
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`<- 24
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31 -<- 16 -<- 9
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`<- 25
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4-Element Loop:
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28 ->- 19 ->- 6 ->- 13 ->- 28
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8 Lead-Ins:
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6 -<- 3 -<- 4
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`<- 20
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13 -<- 22 -<- 11
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`<- 27
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19 -<- 12 -<- 5
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`<- 21
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28 -<- 29 -<- 14
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`<- 30
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Loop Membership:
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(31, 26, 17, 0) |***....****....****....****....*|
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(28, 19, 6, 13) |...****....****....****....****.|
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```
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We can see that there are two distinct sets of states. The assertion `state != 0` holds
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because the init state 27 is in the second set of states, and the zero-state is in the
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first set of states. Let's call the `state != 0` property `p0`:
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```SystemVerilog
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let p0 = (state != 0);
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```
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So `p0` is a true invariant for our circuit, but it is not an inductive invariant,
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because we can go from a state for which `p0` is true to a state for which it is
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false. Specifically there are two such states for this circuit: 1 and 17
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(The property `p0` is k-inductive for k=6, but for this example we are
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only interested in proofs via 1-induction.)
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The following property however would be inductive, as can be easily confirmed
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by looking up the 4 states in the state chart above.
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```SystemVerilog
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let p1 = (state == 28 || state == 19 || state == 6 || state == 13);
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```
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Or, using more fancy SystemVerilog syntax:
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```SystemVerilog
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let p1 = (state inside {28, 19, 6, 13});
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```
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But `p1` is not an invariant of our circuit, as can be easily seen: The initial
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state 27 is not one of the 4 states included in our property.
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We can of course add additional states to our property until it covers the entire
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path from the initial state to state 13:
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```SystemVerilog
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let p2 = (state inside {28, 19, 6, 13, 22, 27});
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```
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The property `p2` is an inductive invariant. Actually, it is an exact
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description of the reachable state space. (As such it is by definition an
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invariant of the circuit, and inductive.)
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However, in real-world verification problems we can't usually enumerate states
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like this. Instead, we need to find more generic functions that are inductive
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invariants of the circuit. In almost all cases those will be functions that
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over-estimate the set of reachable states, instead of describing it exact.
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One such function for the above design would be the following property.
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```SystemVerilog
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let p3 = (state[0] & state[1]) ^ state[2];
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```
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The SBY file [prove_p23.sby](prove_p23.sby) demonstrates how to prove that `p2`
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and `p3` are inductive invariants. (Trying to prove `p0` or `p1` in that manner
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fails, as they are not inductive invariants.)
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And finally [prove_p0.sby](prove_p0.sby) demonstrates how to prove the original
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property `p0`, using the inductive invariants we found to strengthen the proof.
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