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Krystine Sherwin 10332e8e74
btor2aiger: It kinda works? 
- Add `btor2aig_yw.py` to wrap btor2aiger calls, splitting the symbol map into a
  `.aim` file and building (and approximation of) the `.ywa` file.
- Currently not tracking asserts/assumes in the `.ywa`, and yosys-witness isn't
  the biggest fan of the btor2aiger style of unitialised latches.  As such, the
  latches are declared but the `.yw` output doesn't do anything with them so
  it's incomplete.  But the vcd output seems fine (for `vcd_sim=on|off`).
- Add a try/except to catch property matching with an incomplete property list.
- Add `-x` flag to `write_btor` call since aiw2yw gets confused without them.
- Includes some TODO reminders for me to fix things, but as far as I can tell it
  is working.
2024-04-06 13:40:00 +13:00
.github/workflows Update workflows 2024-01-29 08:48:29 +01:00
docs Add dft/data_diode example 2023-09-28 18:59:27 +02:00
extern Fixed names and links 2021-10-31 14:42:39 +01:00
sbysrc btor2aiger: It kinda works? 2024-04-06 13:40:00 +13:00
tests Replace the 'primes' test in junit_timeout_error.sby with a new test that solves a**3 + b**3 == c**3. 2024-04-02 11:28:54 +01:00
tools btor2aiger: It kinda works? 2024-04-06 13:40:00 +13:00
.gitignore Add aiger engine 2017-02-19 23:53:01 +01:00
.readthedocs.yaml Update .readthedocs.yaml 2023-05-08 11:33:14 +02:00
COPYING Fixed names and links 2021-10-31 14:42:39 +01:00
Makefile Fix PREFIX in makefile to accept environment variable, if set 2023-12-02 00:05:05 +00:00
README.md mention tabby+oss cad suite in readme 2022-01-04 16:32:59 +01:00

README.md

SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See https://yosyshq.readthedocs.io/projects/sby/ for documentation on how to use SymbiYosys.

SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.

SymbiYosys (sby) is part of the Tabby CAD Suite and the OSS CAD Suite! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.

Make sure to get a Tabby CAD Suite Evaluation License for extensive SystemVerilog Assertion (SVA) support, as well as industry-grade SystemVerilog and VHDL parsers!

For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet.