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10332e8e74
- Add `btor2aig_yw.py` to wrap btor2aiger calls, splitting the symbol map into a `.aim` file and building (and approximation of) the `.ywa` file. - Currently not tracking asserts/assumes in the `.ywa`, and yosys-witness isn't the biggest fan of the btor2aiger style of unitialised latches. As such, the latches are declared but the `.yw` output doesn't do anything with them so it's incomplete. But the vcd output seems fine (for `vcd_sim=on|off`). - Add a try/except to catch property matching with an incomplete property list. - Add `-x` flag to `write_btor` call since aiw2yw gets confused without them. - Includes some TODO reminders for me to fix things, but as far as I can tell it is working. |
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| .. | ||
| sby.py | ||
| sby_autotune.py | ||
| sby_cmdline.py | ||
| sby_core.py | ||
| sby_design.py | ||
| sby_engine_abc.py | ||
| sby_engine_aiger.py | ||
| sby_engine_btor.py | ||
| sby_engine_smtbmc.py | ||
| sby_jobserver.py | ||
| sby_mode_bmc.py | ||
| sby_mode_cover.py | ||
| sby_mode_live.py | ||
| sby_mode_prove.py | ||
| sby_sim.py | ||
| sby_status.py | ||