mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-27 15:35:51 +00:00
Code Activity

Improve documentation of scripts and Verific bindings

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-23 18:25:52 +02:00
parent 983f066445
commit 93e7e1d1e2
3 changed files with 46 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

27
docs/source/verilog.rst
View file

@ -4,7 +4,9 @@ Formal extensions to Verilog
TBD
``read_verilog -formal``
``read -sv``
``read_verilog -sv``
SystemVerilog Immediate Assertions
----------------------------------
@ -33,17 +35,32 @@ Liveness and Fairness
TBD
``assert(eventually <expr>);``
``assert property (eventually <expr>);``
``assume(eventually <expr>);``
``assume property (eventually <expr>);``
Unconstrained Variables
-----------------------
TBD
Nonstandard Extensions in Yosys
-------------------------------
``(* anyconst *)``
``(* anyseq *)``
``(* allconst *)``
``(* allseq *)``
Global Clock
------------
TBD
``(* gclk *)``
SystemVerilog Concurrent Assertions
-----------------------------------
TBD, see :ref:`sva`.