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67 lines
746 B
ReStructuredText
67 lines
746 B
ReStructuredText
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Formal extensions to Verilog
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============================
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TBD
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``read -sv``
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``read_verilog -sv``
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SystemVerilog Immediate Assertions
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----------------------------------
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TBD
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``assert(<expr>);``
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``assume(<expr>);``
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``cover(<expr>);``
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SystemVerilog Functions
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-----------------------
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TBD
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``$past``
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``$stable``
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``$rose``, ``$fell``
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Liveness and Fairness
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---------------------
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TBD
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``assert property (eventually <expr>);``
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``assume property (eventually <expr>);``
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Unconstrained Variables
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-----------------------
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TBD
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``(* anyconst *)``
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``(* anyseq *)``
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``(* allconst *)``
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``(* allseq *)``
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Global Clock
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------------
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TBD
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``(* gclk *)``
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SystemVerilog Concurrent Assertions
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-----------------------------------
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TBD, see :ref:`sva`.
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