btor2aiger: It kinda works?

- Add `btor2aig_yw.py` to wrap btor2aiger calls, splitting the symbol map into a
  `.aim` file and building (and approximation of) the `.ywa` file.
- Currently not tracking asserts/assumes in the `.ywa`, and yosys-witness isn't
  the biggest fan of the btor2aiger style of unitialised latches.  As such, the
  latches are declared but the `.yw` output doesn't do anything with them so
  it's incomplete.  But the vcd output seems fine (for `vcd_sim=on|off`).
- Add a try/except to catch property matching with an incomplete property list.
- Add `-x` flag to `write_btor` call since aiw2yw gets confused without them.
- Includes some TODO reminders for me to fix things, but as far as I can tell it
  is working.

sbysrc/sby_core.py

@@ -1137,7 +1137,8 @@ class SbyTask(SbyConfig):
                 print("delete -output", file=f)
                 print("dffunmap", file=f)
                 print("stat", file=f)
-                print("write_btor {}-i design_{m}.info -ywmap design_btor.ywb design_{m}.btor".format("-c " if self.opt_mode == "cover" else "", m=model_name), file=f)
+                #TODO: put -x in a conditional
+                print("write_btor -x {}-i design_{m}.info -ywmap design_btor.ywb design_{m}.btor".format("-c " if self.opt_mode == "cover" else "", m=model_name), file=f)
                 print("write_btor -s {}-i design_{m}_single.info -ywmap design_btor_single.ywb design_{m}_single.btor".format("-c " if self.opt_mode == "cover" else "", m=model_name), file=f)
 
             proc = SbyProc(
@@ -1151,15 +1152,14 @@ class SbyTask(SbyConfig):
             return [proc]
 
         if model_name == "aig" and self.opt_btor_aig:
-            #TODO: split .aim from .aig?
-            #TODO: figure out .ywa
-            # Going via btor seems to lose the seqs, not sure how important they are
+            #TODO: aiw2yw doesn't know what to do with the latches
             btor_model = "btor_nomem"
             proc = SbyProc(
                 self,
                 "btor_aig",
                 self.model(btor_model),
-                f"""cd {self.workdir}/model; btor2aiger design_{btor_model}.btor > design_aiger.aig"""
+                #TODO: fix hardcoded path
+                f"cd {self.workdir}/model; python3 ~/sby/tools/btor2aig_yw/btor2aig_yw.py design_{btor_model}.btor"
             )
             proc.checkretcode = True
 

sbysrc/sby_engine_abc.py

@@ -166,7 +166,10 @@ def run(mode, task, engine_idx, engine):
             match = re.match(r"Writing CEX for output ([0-9]+) to engine_[0-9]+/(.*)\.aiw", line)
             if match:
                 output = int(match[1])
-                prop = aiger_props[output]
+                try:
+                    prop = aiger_props[output]
+                except IndexError:
+                    prop = None
                 if prop:
                     prop.status = "FAIL"
                     task.status_db.set_task_property_status(prop, data=dict(source="abc pdr",  engine=f"engine_{engine_idx}"))
@@ -185,7 +188,10 @@ def run(mode, task, engine_idx, engine):
         match = re.match(r"^Proved output +([0-9]+) in frame +-?[0-9]+", line)
         if match:
             output = int(match[1])
-            prop = aiger_props[output]
+            try:
+                prop = aiger_props[output]
+            except IndexError:
+                prop = None
             if prop:
                 prop.status = "PASS"
                 task.status_db.set_task_property_status(prop, data=dict(source="abc pdr",  engine=f"engine_{engine_idx}"))