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NLnet 2024-12-324 Create a model of the instruction fetch/decode control system, using procedural implementations of the most complex HDL modules where appropriate.

#13 by programmerjake was closed 2025-12-17 07:55:08 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs

NLnet 2024-12-324 Create the PowerISA decoder

#12 by programmerjake was closed 2026-01-29 02:23:38 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs

NLnet 2024-12-324 Create the fetch and i-cache logic.

#11 by programmerjake was closed 2026-02-22 21:32:50 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs

NLnet 2024-12-324 Create the next-instruction logic

#10 by programmerjake was closed 2025-12-17 07:55:08 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs

NLnet 2024-12-324 Add to the simulator in Fayalite the ability to transfer non-HDL data (e.g. HashMap) through the digital signalling mechanism, this allows using those data types when writing procedural models.

#7 by programmerjake was closed 2025-09-09 05:35:24 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs

NLnet 2024-12-324 Add support for the Arty A7 100T since that's what we're using for CI.

#6 by programmerjake was closed 2025-10-22 05:36:13 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs

NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).

#4 by programmerjake was closed 2025-10-22 05:36:13 +00:00 NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs