History

Jacob Lifshay cdd84953d0 All checks were successful / deps (pull_request) Successful in 19s Details / test (pull_request) Successful in 3m34s Details / deps (push) Successful in 14s Details / test (push) Successful in 3m58s Details support unknown trait bounds in type parameters		2025-02-13 18:35:30 -08:00
..
examples	change register names to end in `_reg` by convention	2024-10-06 18:50:09 -07:00
src	add #[hdl] let destructuring and, while at it, tuple patterns	2025-02-10 22:49:41 -08:00
tests	support unknown trait bounds in type parameters	2025-02-13 18:35:30 -08:00
build.rs	add test for cfgs	2024-12-28 23:39:50 -08:00
Cargo.toml	simulator WIP: use petgraph for topological sort over assignments	2024-11-20 22:53:54 -08:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	make ClockDomain and Reg generic over reset type	2024-11-26 20:47:03 -08:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.