History

Jacob Lifshay 96b3f1fee4 All checks were successful / deps (push) Successful in 17s Details / test (push) Successful in 4m50s Details working on simulator		2024-11-10 22:12:57 -08:00
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examples	change register names to end in `_reg` by convention	2024-10-06 18:50:09 -07:00
src	working on simulator	2024-11-10 22:12:57 -08:00
tests	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
build.rs	WIP: use HdlOption[the_type_var] or UInt[123 + n] for creating types	2024-08-21 22:27:21 -07:00
Cargo.toml	working on simulator	2024-11-10 22:12:57 -08:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created	2024-10-07 19:06:01 -07:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.