681 lines
27 KiB
Plaintext
681 lines
27 KiB
Plaintext
Simulation {
|
|
state: State {
|
|
insns: Insns {
|
|
state_layout: StateLayout {
|
|
ty: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 4,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 13,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
|
|
ty: SyncReset,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
memories: StatePartLayout<Memories> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
insns: [
|
|
// at: module-XXXXXXXXXX.rs:13:1
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:12:1
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:10:1
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:8:1
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:6:1
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
Const {
|
|
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
|
value: 0,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
|
|
},
|
|
AndSmall {
|
|
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
|
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
BranchIfSmallZero {
|
|
target: 14,
|
|
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
BranchIfSmallNonZero {
|
|
target: 13,
|
|
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
|
},
|
|
Branch {
|
|
target: 14,
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:7:1
|
|
BranchIfSmallZero {
|
|
target: 19,
|
|
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
BranchIfSmallNonZero {
|
|
target: 18,
|
|
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
|
},
|
|
Branch {
|
|
target: 19,
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:9:1
|
|
BranchIfSmallZero {
|
|
target: 24,
|
|
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
BranchIfSmallNonZero {
|
|
target: 23,
|
|
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
|
},
|
|
Branch {
|
|
target: 24,
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:11:1
|
|
BranchIfSmallZero {
|
|
target: 29,
|
|
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
BranchIfSmallNonZero {
|
|
target: 28,
|
|
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
|
},
|
|
Branch {
|
|
target: 29,
|
|
},
|
|
Copy {
|
|
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
NotSmall {
|
|
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 30,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
18446744073709551614,
|
|
0,
|
|
1,
|
|
0,
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::shift_register,
|
|
instantiated: Module {
|
|
name: shift_register,
|
|
..
|
|
},
|
|
},
|
|
uninitialized_inputs: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::shift_register,
|
|
instantiated: Module {
|
|
name: shift_register,
|
|
..
|
|
},
|
|
}.cd: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 2,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
|
|
ty: SyncReset,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Bundle {
|
|
fields: [
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(0),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(1),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: SyncReset,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SyncReset,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::shift_register,
|
|
instantiated: Module {
|
|
name: shift_register,
|
|
..
|
|
},
|
|
}.cd.clk: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::shift_register,
|
|
instantiated: Module {
|
|
name: shift_register,
|
|
..
|
|
},
|
|
}.cd.rst: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: SyncReset,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SyncReset,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::shift_register,
|
|
instantiated: Module {
|
|
name: shift_register,
|
|
..
|
|
},
|
|
}.d: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::shift_register,
|
|
instantiated: Module {
|
|
name: shift_register,
|
|
..
|
|
},
|
|
}.q: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
},
|
|
made_initial_step: true,
|
|
needs_settle: false,
|
|
trace_decls: TraceModule {
|
|
name: "shift_register",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "cd",
|
|
child: TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(0),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(1),
|
|
name: "rst",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "d",
|
|
child: TraceBool {
|
|
location: TraceScalarId(2),
|
|
name: "d",
|
|
flow: Source,
|
|
},
|
|
ty: Bool,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "q",
|
|
child: TraceBool {
|
|
location: TraceScalarId(3),
|
|
name: "q",
|
|
flow: Sink,
|
|
},
|
|
ty: Bool,
|
|
flow: Sink,
|
|
},
|
|
TraceReg {
|
|
name: "reg0",
|
|
child: TraceBool {
|
|
location: TraceScalarId(4),
|
|
name: "reg0",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceReg {
|
|
name: "reg1",
|
|
child: TraceBool {
|
|
location: TraceScalarId(5),
|
|
name: "reg1",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceReg {
|
|
name: "reg2",
|
|
child: TraceBool {
|
|
location: TraceScalarId(6),
|
|
name: "reg2",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceReg {
|
|
name: "reg3",
|
|
child: TraceBool {
|
|
location: TraceScalarId(7),
|
|
name: "reg3",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
],
|
|
trace_memories: {},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 66 μs,
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
],
|
|
} |