310 lines
9.6 KiB
Plaintext
310 lines
9.6 KiB
Plaintext
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 3,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::o",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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0: Return,
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],
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..
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},
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pc: 0,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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0,
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1,
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101,
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],
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},
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},
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io: Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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},
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main_module: SimulationModuleState {
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base_targets: [
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Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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}.en,
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Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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}.clk,
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Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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}.o,
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],
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uninitialized_ios: {},
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io_targets: {
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Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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}.clk,
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Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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}.en,
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Instance {
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name: <simulator>::extern_module2,
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instantiated: Module {
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name: extern_module2,
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..
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},
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}.o,
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},
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did_initial_settle: true,
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},
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extern_modules: [
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SimulationExternModuleState {
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module_state: SimulationModuleState {
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base_targets: [
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ModuleIO {
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name: extern_module2::en,
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is_input: true,
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ty: Bool,
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..
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},
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ModuleIO {
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name: extern_module2::clk,
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is_input: true,
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ty: Clock,
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..
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},
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ModuleIO {
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name: extern_module2::o,
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is_input: false,
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ty: UInt<8>,
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..
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},
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],
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uninitialized_ios: {},
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io_targets: {
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ModuleIO {
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name: extern_module2::clk,
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is_input: true,
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ty: Clock,
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..
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},
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ModuleIO {
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name: extern_module2::en,
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is_input: true,
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ty: Bool,
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..
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},
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ModuleIO {
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name: extern_module2::o,
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is_input: false,
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ty: UInt<8>,
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..
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},
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},
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did_initial_settle: true,
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},
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sim: ExternModuleSimulation {
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generator: SimGeneratorFn {
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args: (
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ModuleIO {
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name: extern_module2::en,
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is_input: true,
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ty: Bool,
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..
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},
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ModuleIO {
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name: extern_module2::clk,
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is_input: true,
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ty: Clock,
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..
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},
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ModuleIO {
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name: extern_module2::o,
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is_input: false,
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ty: UInt<8>,
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..
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},
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),
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f: ...,
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},
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source_location: SourceLocation(
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module-XXXXXXXXXX.rs:5:1,
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),
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},
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running_generator: Some(
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...,
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),
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wait_targets: {
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Change {
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key: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
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ty: Clock,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
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},
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write: None,
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},
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value: SimValue {
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ty: Clock,
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value: OpaqueSimValue {
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bits: 0x1_u1,
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},
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},
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},
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},
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},
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],
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state_ready_to_run: false,
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trace_decls: TraceModule {
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name: "extern_module2",
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children: [
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TraceModuleIO {
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name: "en",
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child: TraceBool {
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location: TraceScalarId(0),
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name: "en",
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flow: Source,
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},
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ty: Bool,
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flow: Source,
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},
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TraceModuleIO {
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name: "clk",
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child: TraceClock {
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location: TraceScalarId(1),
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name: "clk",
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flow: Source,
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},
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ty: Clock,
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flow: Source,
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},
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TraceModuleIO {
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name: "o",
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child: TraceUInt {
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location: TraceScalarId(2),
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name: "o",
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ty: UInt<8>,
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flow: Sink,
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},
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ty: UInt<8>,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(0),
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigClock {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x1,
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last_state: 0x1,
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},
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SimTrace {
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id: TraceScalarId(2),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(2),
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ty: UInt<8>,
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},
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state: 0x65,
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last_state: 0x65,
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},
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],
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trace_memories: {},
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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instant: 60 μs,
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clocks_triggered: [],
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..
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} |